1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CSS_DEF_H__ 32 #define __CSS_DEF_H__ 33 34 #include <arm_def.h> 35 #include <tzc400.h> 36 37 /************************************************************************* 38 * Definitions common to all ARM Compute SubSystems (CSS) 39 *************************************************************************/ 40 #define MHU_PAYLOAD_CACHED 0 41 42 #define NSROM_BASE 0x1f000000 43 #define NSROM_SIZE 0x00001000 44 45 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 46 #define CSS_DEVICE_BASE 0x20000000 47 #define CSS_DEVICE_SIZE 0x0e000000 48 #define MHU_BASE 0x2b1f0000 49 50 #define NSRAM_BASE 0x2e000000 51 #define NSRAM_SIZE 0x00008000 52 53 /* System Security Control Registers */ 54 #define SSC_REG_BASE 0x2a420000 55 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 56 57 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 58 #define CSS_NIC400_SLAVE_BOOTSECURE 8 59 60 /* Interrupt handling constants */ 61 #define CSS_IRQ_MHU 69 62 #define CSS_IRQ_GPU_SMMU_0 71 63 #define CSS_IRQ_TZC 80 64 #define CSS_IRQ_TZ_WDOG 86 65 #define CSS_IRQ_SEC_SYS_TIMER 91 66 67 /* 68 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 69 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 70 */ 71 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 72 CSS_IRQ_GPU_SMMU_0, \ 73 CSS_IRQ_TZC, \ 74 CSS_IRQ_TZ_WDOG, \ 75 CSS_IRQ_SEC_SYS_TIMER 76 77 /* 78 * SCP <=> AP boot configuration 79 * 80 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 81 * the start of the Trusted SRAM. 82 * 83 * Note that the value stored at this address is only valid at boot time, before 84 * the SCP_BL2 image is transferred to SCP. 85 */ 86 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 87 88 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 89 CSS_DEVICE_BASE, \ 90 CSS_DEVICE_SIZE, \ 91 MT_DEVICE | MT_RW | MT_SECURE) 92 93 94 /************************************************************************* 95 * Required platform porting definitions common to all 96 * ARM Compute SubSystems (CSS) 97 ************************************************************************/ 98 99 /* 100 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 101 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 102 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 103 * an SCP_BL2/SCP_BL2U image. 104 */ 105 #if CSS_LOAD_SCP_IMAGES 106 /* 107 * Load address of SCP_BL2 in CSS platform ports 108 * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the 109 * SCP, it is discarded and BL31 is loaded over the top. 110 */ 111 #define SCP_BL2_BASE BL31_BASE 112 113 #define SCP_BL2U_BASE BL31_BASE 114 #endif /* CSS_LOAD_SCP_IMAGES */ 115 116 #define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED 117 118 /* Load address of Non-Secure Image for CSS platform ports */ 119 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 120 121 /* TZC related constants */ 122 #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL 123 #define PLAT_ARM_TZC_BASE 0x2a4a0000 124 125 /* System timer related constants */ 126 #define PLAT_ARM_NSTIMER_FRAME_ID 1 127 128 /* Trusted mailbox base address common to all CSS */ 129 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 130 131 132 #endif /* __CSS_DEF_H__ */ 133