1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CSS_DEF_H__ 32 #define __CSS_DEF_H__ 33 34 #include <arm_def.h> 35 #include <tzc400.h> 36 37 /************************************************************************* 38 * Definitions common to all ARM Compute SubSystems (CSS) 39 *************************************************************************/ 40 #define MHU_PAYLOAD_CACHED 0 41 42 #define NSROM_BASE 0x1f000000 43 #define NSROM_SIZE 0x00001000 44 45 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 46 #define CSS_DEVICE_BASE 0x20000000 47 #define CSS_DEVICE_SIZE 0x0e000000 48 #define MHU_BASE 0x2b1f0000 49 50 #define NSRAM_BASE 0x2e000000 51 #define NSRAM_SIZE 0x00008000 52 53 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 54 #define CSS_NIC400_SLAVE_BOOTSECURE 8 55 56 /* Interrupt handling constants */ 57 #define CSS_IRQ_MHU 69 58 #define CSS_IRQ_GPU_SMMU_0 71 59 #define CSS_IRQ_TZC 80 60 #define CSS_IRQ_TZ_WDOG 86 61 #define CSS_IRQ_SEC_SYS_TIMER 91 62 63 /* 64 * SCP <=> AP boot configuration 65 * 66 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 67 * the start of the Trusted SRAM. Part of this configuration is which CPU is the 68 * primary, according to the shift and mask definitions below. 69 * 70 * Note that the value stored at this address is only valid at boot time, before 71 * the BL3-0 image is transferred to SCP. 72 */ 73 #define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) 74 #define PRIMARY_CPU_SHIFT 8 75 #define PRIMARY_CPU_BIT_WIDTH 4 76 77 /* 78 * Base address of the first memory region used for communication between AP 79 * and SCP. Used by the BOM and SCPI protocols. 80 * 81 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 82 * means the SCP/AP configuration data gets overwritten when the AP initiates 83 * communication with the SCP. 84 */ 85 #define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 86 87 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 88 CSS_DEVICE_BASE, \ 89 CSS_DEVICE_SIZE, \ 90 MT_DEVICE | MT_RW | MT_SECURE) 91 92 93 /************************************************************************* 94 * Required platform porting definitions common to all 95 * ARM Compute SubSystems (CSS) 96 ************************************************************************/ 97 98 /* 99 * Load address of BL3-0 in CSS platform ports 100 * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the 101 * SCP, it is discarded and BL3-1 is loaded over the top. 102 */ 103 #define BL30_BASE BL31_BASE 104 105 #define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED 106 107 /* Load address of Non-Secure Image for CSS platform ports */ 108 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 109 110 /* TZC related constants */ 111 #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL 112 #define PLAT_ARM_TZC_BASE 0x2a4a0000 113 114 /* System timer related constants */ 115 #define PLAT_ARM_NSTIMER_FRAME_ID 1 116 117 /* Trusted mailbox base address common to all CSS */ 118 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 119 120 121 #endif /* __CSS_DEF_H__ */ 122