1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CSS_DEF_H__ 32 #define __CSS_DEF_H__ 33 34 #include <arm_def.h> 35 #include <tzc400.h> 36 37 /************************************************************************* 38 * Definitions common to all ARM Compute SubSystems (CSS) 39 *************************************************************************/ 40 #define MHU_PAYLOAD_CACHED 0 41 42 #define NSROM_BASE 0x1f000000 43 #define NSROM_SIZE 0x00001000 44 45 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 46 #define CSS_DEVICE_BASE 0x20000000 47 #define CSS_DEVICE_SIZE 0x0e000000 48 49 #define NSRAM_BASE 0x2e000000 50 #define NSRAM_SIZE 0x00008000 51 52 /* System Security Control Registers */ 53 #define SSC_REG_BASE 0x2a420000 54 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 55 56 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 57 #define CSS_NIC400_SLAVE_BOOTSECURE 8 58 59 /* Interrupt handling constants */ 60 #define CSS_IRQ_MHU 69 61 #define CSS_IRQ_GPU_SMMU_0 71 62 #define CSS_IRQ_TZC 80 63 #define CSS_IRQ_TZ_WDOG 86 64 #define CSS_IRQ_SEC_SYS_TIMER 91 65 66 /* 67 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 68 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 69 */ 70 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 71 CSS_IRQ_GPU_SMMU_0, \ 72 CSS_IRQ_TZC, \ 73 CSS_IRQ_TZ_WDOG, \ 74 CSS_IRQ_SEC_SYS_TIMER 75 76 /* 77 * SCP <=> AP boot configuration 78 * 79 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 80 * the start of the Trusted SRAM. Part of this configuration is which CPU is the 81 * primary, according to the shift and mask definitions below. 82 * 83 * Note that the value stored at this address is only valid at boot time, before 84 * the SCP_BL2 image is transferred to SCP. 85 */ 86 #define SCP_BOOT_CFG_ADDR (ARM_TRUSTED_SRAM_BASE + 0x80) 87 #define PRIMARY_CPU_SHIFT 8 88 #define PRIMARY_CPU_BIT_WIDTH 4 89 90 /* 91 * Base address of the first memory region used for communication between AP 92 * and SCP. Used by the BOM and SCPI protocols. 93 * 94 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 95 * means the SCP/AP configuration data gets overwritten when the AP initiates 96 * communication with the SCP. 97 */ 98 #define SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + 0x80) 99 100 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 101 CSS_DEVICE_BASE, \ 102 CSS_DEVICE_SIZE, \ 103 MT_DEVICE | MT_RW | MT_SECURE) 104 105 /* Platform ID address */ 106 #define SSC_VERSION_OFFSET 0x040 107 108 #define SSC_VERSION_CONFIG_SHIFT 28 109 #define SSC_VERSION_MAJOR_REV_SHIFT 24 110 #define SSC_VERSION_MINOR_REV_SHIFT 20 111 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 112 #define SSC_VERSION_PART_NUM_SHIFT 0x0 113 #define SSC_VERSION_CONFIG_MASK 0xf 114 #define SSC_VERSION_MAJOR_REV_MASK 0xf 115 #define SSC_VERSION_MINOR_REV_MASK 0xf 116 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 117 #define SSC_VERSION_PART_NUM_MASK 0xfff 118 119 #ifndef __ASSEMBLY__ 120 121 /* SSC_VERSION related accessors */ 122 123 /* Returns the part number of the platform */ 124 #define GET_SSC_VERSION_PART_NUM(val) \ 125 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 126 SSC_VERSION_PART_NUM_MASK) 127 128 /* Returns the configuration number of the platform */ 129 #define GET_SSC_VERSION_CONFIG(val) \ 130 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 131 SSC_VERSION_CONFIG_MASK) 132 133 #endif /* __ASSEMBLY__ */ 134 135 /************************************************************************* 136 * Required platform porting definitions common to all 137 * ARM Compute SubSystems (CSS) 138 ************************************************************************/ 139 140 /* 141 * Load address of SCP_BL2 in CSS platform ports 142 * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the 143 * SCP, it is discarded and BL31 is loaded over the top. 144 */ 145 #define SCP_BL2_BASE BL31_BASE 146 147 #define SCP_BL2U_BASE BL31_BASE 148 149 #define PLAT_ARM_SHARED_RAM_CACHED MHU_PAYLOAD_CACHED 150 151 /* Load address of Non-Secure Image for CSS platform ports */ 152 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 153 154 /* TZC related constants */ 155 #define PLAT_ARM_TZC_FILTERS REG_ATTR_FILTER_BIT_ALL 156 157 /* Trusted mailbox base address common to all CSS */ 158 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 159 160 161 #endif /* __CSS_DEF_H__ */ 162