1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __PLAT_ARM_H__ 7 #define __PLAT_ARM_H__ 8 9 #include <arm_xlat_tables.h> 10 #include <bakery_lock.h> 11 #include <cassert.h> 12 #include <cpu_data.h> 13 #include <stdint.h> 14 #include <tzc_common.h> 15 #include <utils_def.h> 16 17 /******************************************************************************* 18 * Forward declarations 19 ******************************************************************************/ 20 struct bl31_params; 21 struct meminfo; 22 struct image_info; 23 struct bl_params; 24 25 typedef struct arm_tzc_regions_info { 26 unsigned long long base; 27 unsigned long long end; 28 tzc_region_attributes_t sec_attr; 29 unsigned int nsaid_permissions; 30 } arm_tzc_regions_info_t; 31 32 /******************************************************************************* 33 * Default mapping definition of the TrustZone Controller for ARM standard 34 * platforms. 35 * Configure: 36 * - Region 0 with no access; 37 * - Region 1 with secure access only; 38 * - the remaining DRAM regions access from the given Non-Secure masters. 39 ******************************************************************************/ 40 #if ENABLE_SPM 41 #define ARM_TZC_REGIONS_DEF \ 42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 43 TZC_REGION_S_RDWR, 0}, \ 44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ 49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 50 PLAT_ARM_TZC_NS_DEV_ACCESS} 51 52 #else 53 #define ARM_TZC_REGIONS_DEF \ 54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 55 TZC_REGION_S_RDWR, 0}, \ 56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS} 60 #endif 61 62 #define ARM_CASSERT_MMAP \ 63 CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ 64 <= MAX_MMAP_REGIONS, \ 65 assert_max_mmap_regions); 66 67 /* 68 * Utility functions common to ARM standard platforms 69 */ 70 void arm_setup_page_tables(uintptr_t total_base, 71 size_t total_size, 72 uintptr_t code_start, 73 uintptr_t code_limit, 74 uintptr_t rodata_start, 75 uintptr_t rodata_limit 76 #if USE_COHERENT_MEM 77 , uintptr_t coh_start, 78 uintptr_t coh_limit 79 #endif 80 ); 81 82 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) 83 /* 84 * Use this macro to instantiate lock before it is used in below 85 * arm_lock_xxx() macros 86 */ 87 #define ARM_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_lock) 88 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 89 /* 90 * These are wrapper macros to the Coherent Memory Bakery Lock API. 91 */ 92 #define arm_lock_init() bakery_lock_init(&arm_lock) 93 #define arm_lock_get() bakery_lock_get(&arm_lock) 94 #define arm_lock_release() bakery_lock_release(&arm_lock) 95 96 #else 97 98 /* 99 * Empty macros for all other BL stages other than BL31 and BL32 100 */ 101 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 102 #define ARM_LOCK_GET_INSTANCE 0 103 #define arm_lock_init() 104 #define arm_lock_get() 105 #define arm_lock_release() 106 107 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ 108 109 #if ARM_RECOM_STATE_ID_ENC 110 /* 111 * Macros used to parse state information from State-ID if it is using the 112 * recommended encoding for State-ID. 113 */ 114 #define ARM_LOCAL_PSTATE_WIDTH 4 115 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 116 117 /* Macros to construct the composite power state */ 118 119 /* Make composite power state parameter till power level 0 */ 120 #if PSCI_EXTENDED_STATE_ID 121 122 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 123 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 124 #else 125 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 126 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 127 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 128 ((type) << PSTATE_TYPE_SHIFT)) 129 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 130 131 /* Make composite power state parameter till power level 1 */ 132 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 133 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 134 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 135 136 /* Make composite power state parameter till power level 2 */ 137 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 138 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 139 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 140 141 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 142 143 /* ARM State switch error codes */ 144 #define STATE_SW_E_PARAM (-2) 145 #define STATE_SW_E_DENIED (-3) 146 147 /* IO storage utility functions */ 148 void arm_io_setup(void); 149 150 /* Security utility functions */ 151 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); 152 struct tzc_dmc500_driver_data; 153 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 154 const arm_tzc_regions_info_t *tzc_regions); 155 156 /* Systimer utility function */ 157 void arm_configure_sys_timer(void); 158 159 /* PM utility functions */ 160 int arm_validate_power_state(unsigned int power_state, 161 psci_power_state_t *req_state); 162 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 163 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 164 void arm_system_pwr_domain_save(void); 165 void arm_system_pwr_domain_resume(void); 166 void arm_program_trusted_mailbox(uintptr_t address); 167 int arm_psci_read_mem_protect(int *enabled); 168 int arm_nor_psci_write_mem_protect(int val); 169 void arm_nor_psci_do_static_mem_protect(void); 170 void arm_nor_psci_do_dyn_mem_protect(void); 171 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 172 173 /* Topology utility function */ 174 int arm_check_mpidr(u_register_t mpidr); 175 176 /* BL1 utility functions */ 177 void arm_bl1_early_platform_setup(void); 178 void arm_bl1_platform_setup(void); 179 void arm_bl1_plat_arch_setup(void); 180 181 /* BL2 utility functions */ 182 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 183 void arm_bl2_platform_setup(void); 184 void arm_bl2_plat_arch_setup(void); 185 uint32_t arm_get_spsr_for_bl32_entry(void); 186 uint32_t arm_get_spsr_for_bl33_entry(void); 187 int arm_bl2_handle_post_image_load(unsigned int image_id); 188 189 /* BL2 at EL3 functions */ 190 void arm_bl2_el3_early_platform_setup(void); 191 void arm_bl2_el3_plat_arch_setup(void); 192 193 /* BL2U utility functions */ 194 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 195 void *plat_info); 196 void arm_bl2u_platform_setup(void); 197 void arm_bl2u_plat_arch_setup(void); 198 199 /* BL31 utility functions */ 200 #if LOAD_IMAGE_V2 201 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 202 uintptr_t hw_config, void *plat_params_from_bl2); 203 #else 204 void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config, 205 uintptr_t hw_config, void *plat_params_from_bl2); 206 #endif /* LOAD_IMAGE_V2 */ 207 void arm_bl31_platform_setup(void); 208 void arm_bl31_plat_runtime_setup(void); 209 void arm_bl31_plat_arch_setup(void); 210 211 /* TSP utility functions */ 212 void arm_tsp_early_platform_setup(void); 213 214 /* SP_MIN utility functions */ 215 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 216 uintptr_t hw_config, void *plat_params_from_bl2); 217 void arm_sp_min_plat_runtime_setup(void); 218 219 /* FIP TOC validity check */ 220 int arm_io_is_toc_valid(void); 221 222 /* Utility functions for Dynamic Config */ 223 void arm_load_tb_fw_config(void); 224 void arm_bl2_set_tb_cfg_addr(void *dtb); 225 void arm_bl2_dyn_cfg_init(void); 226 227 /* 228 * Mandatory functions required in ARM standard platforms 229 */ 230 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 231 void plat_arm_gic_driver_init(void); 232 void plat_arm_gic_init(void); 233 void plat_arm_gic_cpuif_enable(void); 234 void plat_arm_gic_cpuif_disable(void); 235 void plat_arm_gic_redistif_on(void); 236 void plat_arm_gic_redistif_off(void); 237 void plat_arm_gic_pcpu_init(void); 238 void plat_arm_gic_save(void); 239 void plat_arm_gic_resume(void); 240 void plat_arm_security_setup(void); 241 void plat_arm_pwrc_setup(void); 242 void plat_arm_interconnect_init(void); 243 void plat_arm_interconnect_enter_coherency(void); 244 void plat_arm_interconnect_exit_coherency(void); 245 246 #if ARM_PLAT_MT 247 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 248 #endif 249 250 #if LOAD_IMAGE_V2 251 /* 252 * This function is called after loading SCP_BL2 image and it is used to perform 253 * any platform-specific actions required to handle the SCP firmware. 254 */ 255 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 256 #endif 257 258 /* 259 * Optional functions required in ARM standard platforms 260 */ 261 void plat_arm_io_setup(void); 262 int plat_arm_get_alt_image_source( 263 unsigned int image_id, 264 uintptr_t *dev_handle, 265 uintptr_t *image_spec); 266 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 267 const mmap_region_t *plat_arm_get_mmap(void); 268 269 /* Allow platform to override psci_pm_ops during runtime */ 270 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 271 272 /* Execution state switch in ARM platforms */ 273 int arm_execution_state_switch(unsigned int smc_fid, 274 uint32_t pc_hi, 275 uint32_t pc_lo, 276 uint32_t cookie_hi, 277 uint32_t cookie_lo, 278 void *handle); 279 280 /* Optional functions for SP_MIN */ 281 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 282 u_register_t arg2, u_register_t arg3); 283 284 /* global variables */ 285 extern plat_psci_ops_t plat_arm_psci_pm_ops; 286 extern const mmap_region_t plat_arm_mmap[]; 287 288 #endif /* __PLAT_ARM_H__ */ 289