1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __PLAT_ARM_H__ 7 #define __PLAT_ARM_H__ 8 9 #include <arm_xlat_tables.h> 10 #include <bakery_lock.h> 11 #include <cassert.h> 12 #include <cpu_data.h> 13 #include <stdint.h> 14 #include <tzc_common.h> 15 #include <utils_def.h> 16 17 /******************************************************************************* 18 * Forward declarations 19 ******************************************************************************/ 20 struct bl31_params; 21 struct meminfo; 22 struct image_info; 23 struct bl_params; 24 25 typedef struct arm_tzc_regions_info { 26 unsigned long long base; 27 unsigned long long end; 28 tzc_region_attributes_t sec_attr; 29 unsigned int nsaid_permissions; 30 } arm_tzc_regions_info_t; 31 32 /******************************************************************************* 33 * Default mapping definition of the TrustZone Controller for ARM standard 34 * platforms. 35 * Configure: 36 * - Region 0 with no access; 37 * - Region 1 with secure access only; 38 * - the remaining DRAM regions access from the given Non-Secure masters. 39 ******************************************************************************/ 40 #if ENABLE_SPM 41 #define ARM_TZC_REGIONS_DEF \ 42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 43 TZC_REGION_S_RDWR, 0}, \ 44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ 49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 50 PLAT_ARM_TZC_NS_DEV_ACCESS} 51 52 #else 53 #define ARM_TZC_REGIONS_DEF \ 54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 55 TZC_REGION_S_RDWR, 0}, \ 56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS} 60 #endif 61 62 #define ARM_CASSERT_MMAP \ 63 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 64 assert_plat_arm_mmap_mismatch); \ 65 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 66 <= MAX_MMAP_REGIONS, \ 67 assert_max_mmap_regions); 68 69 /* 70 * Utility functions common to ARM standard platforms 71 */ 72 void arm_setup_page_tables(const mmap_region_t bl_regions[], 73 const mmap_region_t plat_regions[]); 74 75 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) 76 /* 77 * Use this macro to instantiate lock before it is used in below 78 * arm_lock_xxx() macros 79 */ 80 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 81 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 82 /* 83 * These are wrapper macros to the Coherent Memory Bakery Lock API. 84 */ 85 #define arm_lock_init() bakery_lock_init(&arm_lock) 86 #define arm_lock_get() bakery_lock_get(&arm_lock) 87 #define arm_lock_release() bakery_lock_release(&arm_lock) 88 89 #else 90 91 /* 92 * Empty macros for all other BL stages other than BL31 and BL32 93 */ 94 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 95 #define ARM_LOCK_GET_INSTANCE 0 96 #define arm_lock_init() 97 #define arm_lock_get() 98 #define arm_lock_release() 99 100 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ 101 102 #if ARM_RECOM_STATE_ID_ENC 103 /* 104 * Macros used to parse state information from State-ID if it is using the 105 * recommended encoding for State-ID. 106 */ 107 #define ARM_LOCAL_PSTATE_WIDTH 4 108 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 109 110 /* Macros to construct the composite power state */ 111 112 /* Make composite power state parameter till power level 0 */ 113 #if PSCI_EXTENDED_STATE_ID 114 115 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 116 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 117 #else 118 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 119 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 120 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 121 ((type) << PSTATE_TYPE_SHIFT)) 122 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 123 124 /* Make composite power state parameter till power level 1 */ 125 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 126 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 127 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 128 129 /* Make composite power state parameter till power level 2 */ 130 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 131 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 132 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 133 134 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 135 136 /* ARM State switch error codes */ 137 #define STATE_SW_E_PARAM (-2) 138 #define STATE_SW_E_DENIED (-3) 139 140 /* IO storage utility functions */ 141 void arm_io_setup(void); 142 143 /* Security utility functions */ 144 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); 145 struct tzc_dmc500_driver_data; 146 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 147 const arm_tzc_regions_info_t *tzc_regions); 148 149 /* Console utility functions */ 150 void arm_console_boot_init(void); 151 void arm_console_boot_end(void); 152 void arm_console_runtime_init(void); 153 void arm_console_runtime_end(void); 154 155 /* Systimer utility function */ 156 void arm_configure_sys_timer(void); 157 158 /* PM utility functions */ 159 int arm_validate_power_state(unsigned int power_state, 160 psci_power_state_t *req_state); 161 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 162 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 163 void arm_system_pwr_domain_save(void); 164 void arm_system_pwr_domain_resume(void); 165 int arm_psci_read_mem_protect(int *enabled); 166 int arm_nor_psci_write_mem_protect(int val); 167 void arm_nor_psci_do_static_mem_protect(void); 168 void arm_nor_psci_do_dyn_mem_protect(void); 169 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 170 171 /* Topology utility function */ 172 int arm_check_mpidr(u_register_t mpidr); 173 174 /* BL1 utility functions */ 175 void arm_bl1_early_platform_setup(void); 176 void arm_bl1_platform_setup(void); 177 void arm_bl1_plat_arch_setup(void); 178 179 /* BL2 utility functions */ 180 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 181 void arm_bl2_platform_setup(void); 182 void arm_bl2_plat_arch_setup(void); 183 uint32_t arm_get_spsr_for_bl32_entry(void); 184 uint32_t arm_get_spsr_for_bl33_entry(void); 185 int arm_bl2_handle_post_image_load(unsigned int image_id); 186 187 /* BL2 at EL3 functions */ 188 void arm_bl2_el3_early_platform_setup(void); 189 void arm_bl2_el3_plat_arch_setup(void); 190 191 /* BL2U utility functions */ 192 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 193 void *plat_info); 194 void arm_bl2u_platform_setup(void); 195 void arm_bl2u_plat_arch_setup(void); 196 197 /* BL31 utility functions */ 198 #if LOAD_IMAGE_V2 199 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 200 uintptr_t hw_config, void *plat_params_from_bl2); 201 #else 202 void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config, 203 uintptr_t hw_config, void *plat_params_from_bl2); 204 #endif /* LOAD_IMAGE_V2 */ 205 void arm_bl31_platform_setup(void); 206 void arm_bl31_plat_runtime_setup(void); 207 void arm_bl31_plat_arch_setup(void); 208 209 /* TSP utility functions */ 210 void arm_tsp_early_platform_setup(void); 211 212 /* SP_MIN utility functions */ 213 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 214 uintptr_t hw_config, void *plat_params_from_bl2); 215 void arm_sp_min_plat_runtime_setup(void); 216 217 /* FIP TOC validity check */ 218 int arm_io_is_toc_valid(void); 219 220 /* Utility functions for Dynamic Config */ 221 void arm_load_tb_fw_config(void); 222 void arm_bl2_set_tb_cfg_addr(void *dtb); 223 void arm_bl2_dyn_cfg_init(void); 224 225 /* 226 * Mandatory functions required in ARM standard platforms 227 */ 228 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 229 void plat_arm_gic_driver_init(void); 230 void plat_arm_gic_init(void); 231 void plat_arm_gic_cpuif_enable(void); 232 void plat_arm_gic_cpuif_disable(void); 233 void plat_arm_gic_redistif_on(void); 234 void plat_arm_gic_redistif_off(void); 235 void plat_arm_gic_pcpu_init(void); 236 void plat_arm_gic_save(void); 237 void plat_arm_gic_resume(void); 238 void plat_arm_security_setup(void); 239 void plat_arm_pwrc_setup(void); 240 void plat_arm_interconnect_init(void); 241 void plat_arm_interconnect_enter_coherency(void); 242 void plat_arm_interconnect_exit_coherency(void); 243 void plat_arm_program_trusted_mailbox(uintptr_t address); 244 245 #if ARM_PLAT_MT 246 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 247 #endif 248 249 #if LOAD_IMAGE_V2 250 /* 251 * This function is called after loading SCP_BL2 image and it is used to perform 252 * any platform-specific actions required to handle the SCP firmware. 253 */ 254 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 255 #endif 256 257 /* 258 * Optional functions required in ARM standard platforms 259 */ 260 void plat_arm_io_setup(void); 261 int plat_arm_get_alt_image_source( 262 unsigned int image_id, 263 uintptr_t *dev_handle, 264 uintptr_t *image_spec); 265 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 266 const mmap_region_t *plat_arm_get_mmap(void); 267 268 /* Allow platform to override psci_pm_ops during runtime */ 269 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 270 271 /* Execution state switch in ARM platforms */ 272 int arm_execution_state_switch(unsigned int smc_fid, 273 uint32_t pc_hi, 274 uint32_t pc_lo, 275 uint32_t cookie_hi, 276 uint32_t cookie_lo, 277 void *handle); 278 279 /* Optional functions for SP_MIN */ 280 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 281 u_register_t arg2, u_register_t arg3); 282 283 /* global variables */ 284 extern plat_psci_ops_t plat_arm_psci_pm_ops; 285 extern const mmap_region_t plat_arm_mmap[]; 286 extern const unsigned int arm_pm_idle_states[]; 287 288 #endif /* __PLAT_ARM_H__ */ 289