1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLAT_ARM_H 7 #define PLAT_ARM_H 8 9 #include <stdbool.h> 10 #include <stdint.h> 11 12 #include <common/desc_image_load.h> 13 #include <drivers/arm/gic.h> 14 #include <drivers/arm/tzc_common.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/cassert.h> 17 #include <lib/el3_runtime/cpu_data.h> 18 #include <lib/gpt_rme/gpt_rme.h> 19 #include <lib/spinlock.h> 20 #include <lib/utils_def.h> 21 #include <lib/xlat_tables/xlat_tables_compat.h> 22 #if TRANSFER_LIST 23 #include <transfer_list.h> 24 #endif 25 26 /******************************************************************************* 27 * Forward declarations 28 ******************************************************************************/ 29 struct meminfo; 30 struct image_info; 31 struct bl_params; 32 33 typedef struct arm_tzc_regions_info { 34 unsigned long long base; 35 unsigned long long end; 36 unsigned int sec_attr; 37 unsigned int nsaid_permissions; 38 } arm_tzc_regions_info_t; 39 40 typedef struct arm_gpt_info { 41 pas_region_t *pas_region_base; 42 unsigned int pas_region_count; 43 uintptr_t l0_base; 44 uintptr_t l1_base; 45 size_t l0_size; 46 size_t l1_size; 47 gpccr_pps_e pps; 48 gpccr_pgs_e pgs; 49 } arm_gpt_info_t; 50 51 /******************************************************************************* 52 * Default mapping definition of the TrustZone Controller for ARM standard 53 * platforms. 54 * Configure: 55 * - Region 0 with no access; 56 * - Region 1 with secure access only; 57 * - the remaining DRAM regions access from the given Non-Secure masters. 58 ******************************************************************************/ 59 60 #if ENABLE_RME 61 #define ARM_TZC_RME_REGIONS_DEF \ 62 {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\ 63 {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \ 64 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 65 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 66 /* Realm and Shared area share the same PAS */ \ 67 {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 68 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 69 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 70 PLAT_ARM_TZC_NS_DEV_ACCESS} 71 #endif 72 73 #if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) 74 #define ARM_TZC_REGIONS_DEF \ 75 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 76 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 77 {ARM_AP_TZC_DRAM1_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE - 1), \ 78 TZC_REGION_S_RDWR, 0}, \ 79 {PLAT_SP_IMAGE_NS_BUF_BASE, (PLAT_SP_IMAGE_NS_BUF_BASE + \ 80 PLAT_SP_IMAGE_NS_BUF_SIZE - 1), TZC_REGION_S_NONE, \ 81 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 82 {PLAT_SP_IMAGE_STACK_BASE, ARM_EL3_TZC_DRAM1_END, \ 83 TZC_REGION_S_RDWR, 0}, \ 84 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 85 PLAT_ARM_TZC_NS_DEV_ACCESS} 86 87 #elif ENABLE_RME 88 #if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 89 MEASURED_BOOT 90 #define ARM_TZC_REGIONS_DEF \ 91 ARM_TZC_RME_REGIONS_DEF, \ 92 {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \ 93 TZC_REGION_S_RDWR, 0} 94 #else 95 #define ARM_TZC_REGIONS_DEF \ 96 ARM_TZC_RME_REGIONS_DEF 97 #endif 98 99 #else 100 #define ARM_TZC_REGIONS_DEF \ 101 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\ 102 TZC_REGION_S_RDWR, 0}, \ 103 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 104 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 105 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 106 PLAT_ARM_TZC_NS_DEV_ACCESS} 107 #endif 108 109 #define ARM_CASSERT_MMAP \ 110 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 111 assert_plat_arm_mmap_mismatch); \ 112 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 113 <= MAX_MMAP_REGIONS, \ 114 assert_max_mmap_regions); 115 116 void arm_setup_romlib(void); 117 118 #if defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) 119 /* 120 * Use this macro to instantiate lock before it is used in below 121 * arm_lock_xxx() macros 122 */ 123 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 124 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 125 126 #if !HW_ASSISTED_COHERENCY 127 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 128 #else 129 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 130 #endif 131 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 132 133 /* 134 * These are wrapper macros to the Coherent Memory Bakery Lock API. 135 */ 136 #define arm_lock_init() bakery_lock_init(&arm_lock) 137 #define arm_lock_get() bakery_lock_get(&arm_lock) 138 #define arm_lock_release() bakery_lock_release(&arm_lock) 139 140 #else 141 142 /* 143 * Empty macros for all other BL stages other than BL31 and BL32 144 */ 145 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 146 #define ARM_LOCK_GET_INSTANCE 0 147 #define arm_lock_init() 148 #define arm_lock_get() 149 #define arm_lock_release() 150 151 #endif /* defined(IMAGE_BL31) || (!defined(__aarch64__) && defined(IMAGE_BL32)) */ 152 153 #ifdef __aarch64__ 154 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO64 155 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT64 156 #else 157 #define TL_TAG_EXEC_EP_INFO TL_TAG_EXEC_EP_INFO32 158 #define TL_TAG_SRAM_LAYOUT TL_TAG_SRAM_LAYOUT32 159 #endif 160 161 #if ARM_RECOM_STATE_ID_ENC 162 /* 163 * Macros used to parse state information from State-ID if it is using the 164 * recommended encoding for State-ID. 165 */ 166 #define ARM_LOCAL_PSTATE_WIDTH 4 167 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 168 169 /* Last in Level for the OS-initiated */ 170 #define ARM_LAST_AT_PLVL_MASK (ARM_LOCAL_PSTATE_MASK << \ 171 (ARM_LOCAL_PSTATE_WIDTH * \ 172 (PLAT_MAX_PWR_LVL + 1))) 173 174 /* Macros to construct the composite power state */ 175 176 /* Make composite power state parameter till power level 0 */ 177 #if PSCI_EXTENDED_STATE_ID 178 179 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 180 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 181 #else 182 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 183 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 184 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 185 ((type) << PSTATE_TYPE_SHIFT)) 186 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 187 188 /* Make composite power state parameter till power level 1 */ 189 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 190 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 191 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 192 193 /* Make composite power state parameter till power level 2 */ 194 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 195 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 196 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 197 198 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 199 200 /* ARM State switch error codes */ 201 #define STATE_SW_E_PARAM (-2) 202 #define STATE_SW_E_DENIED (-3) 203 204 /* plat_get_rotpk_info() flags */ 205 #define ARM_ROTPK_REGS_ID 1 206 #define ARM_ROTPK_DEVEL_RSA_ID 2 207 #define ARM_ROTPK_DEVEL_ECDSA_ID 3 208 #define ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID 4 209 #define ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID 5 210 211 #define ARM_USE_DEVEL_ROTPK \ 212 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_RSA_ID) || \ 213 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_ECDSA_ID) || \ 214 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_RSA_KEY_ID) || \ 215 (ARM_ROTPK_LOCATION_ID == ARM_ROTPK_DEVEL_FULL_DEV_ECDSA_KEY_ID) 216 217 /* IO storage utility functions */ 218 int arm_io_setup(void); 219 220 /* Set image specification in IO block policy */ 221 int arm_set_image_source(unsigned int image_id, const char *part_name, 222 uintptr_t *dev_handle, uintptr_t *image_spec); 223 void arm_set_fip_addr(uint32_t active_fw_bank_idx); 224 225 /* Security utility functions */ 226 void arm_tzc400_setup(uintptr_t tzc_base, 227 const arm_tzc_regions_info_t *tzc_regions); 228 struct tzc_dmc500_driver_data; 229 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 230 const arm_tzc_regions_info_t *tzc_regions); 231 232 /* Console utility functions */ 233 void arm_console_boot_init(void); 234 void arm_console_boot_end(void); 235 void arm_console_runtime_init(void); 236 void arm_console_runtime_end(void); 237 238 /* Systimer utility function */ 239 void arm_configure_sys_timer(void); 240 241 /* PM utility functions */ 242 int arm_validate_power_state(unsigned int power_state, 243 psci_power_state_t *req_state); 244 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 245 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 246 void arm_system_pwr_domain_save(void); 247 void arm_system_pwr_domain_resume(void); 248 int arm_psci_read_mem_protect(int *enabled); 249 int arm_nor_psci_write_mem_protect(int val); 250 void arm_nor_psci_do_static_mem_protect(void); 251 void arm_nor_psci_do_dyn_mem_protect(void); 252 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 253 254 /* Topology utility function */ 255 int arm_check_mpidr(u_register_t mpidr); 256 257 /* BL1 utility functions */ 258 void arm_bl1_early_platform_setup(void); 259 void arm_bl1_platform_setup(void); 260 void arm_bl1_plat_arch_setup(void); 261 262 /* BL2 utility functions */ 263 void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1, 264 u_register_t arg2, u_register_t arg3); 265 void arm_bl2_platform_setup(void); 266 void arm_bl2_plat_arch_setup(void); 267 uint32_t arm_get_spsr_for_bl32_entry(void); 268 uint32_t arm_get_spsr_for_bl33_entry(void); 269 int arm_bl2_plat_handle_post_image_load(unsigned int image_id); 270 int arm_bl2_handle_post_image_load(unsigned int image_id); 271 struct bl_params *arm_get_next_bl_params(void); 272 void arm_bl2_setup_next_ep_info(bl_mem_params_node_t *next_param_node); 273 274 /* BL2 at EL3 functions */ 275 void arm_bl2_el3_early_platform_setup(void); 276 void arm_bl2_el3_plat_arch_setup(void); 277 #if ARM_FW_CONFIG_LOAD_ENABLE 278 void arm_bl2_el3_plat_config_load(void); 279 #endif /* ARM_FW_CONFIG_LOAD_ENABLE */ 280 281 /* BL2U utility functions */ 282 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 283 void *plat_info); 284 void arm_bl2u_platform_setup(void); 285 void arm_bl2u_plat_arch_setup(void); 286 287 /* BL31 utility functions */ 288 void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, 289 u_register_t arg2, u_register_t arg3); 290 void arm_bl31_platform_setup(void); 291 void arm_bl31_plat_runtime_setup(void); 292 void arm_bl31_plat_arch_setup(void); 293 294 /* Firmware Handoff utility functions */ 295 #if TRANSFER_LIST 296 void arm_transfer_list_dyn_cfg_init(struct transfer_list_header *secure_tl); 297 void arm_transfer_list_populate_ep_info(bl_mem_params_node_t *next_param_node, 298 struct transfer_list_header *secure_tl); 299 void arm_transfer_list_copy_hw_config(struct transfer_list_header *secure_tl, 300 struct transfer_list_header *ns_tl); 301 struct transfer_list_entry * 302 arm_transfer_list_set_heap_info(struct transfer_list_header *tl); 303 void arm_transfer_list_get_heap_info(void **heap_addr, size_t *heap_size); 304 #endif 305 306 /* TSP utility functions */ 307 void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, 308 u_register_t arg2, u_register_t arg3); 309 310 /* SP_MIN utility functions */ 311 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 312 u_register_t arg2, u_register_t arg3); 313 void arm_sp_min_plat_runtime_setup(void); 314 void arm_sp_min_plat_arch_setup(void); 315 316 /* FIP TOC validity check */ 317 bool arm_io_is_toc_valid(void); 318 319 /* Utility functions for Dynamic Config */ 320 321 void arm_bl1_set_mbedtls_heap(void); 322 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 323 324 #if IMAGE_BL2 325 void arm_bl2_dyn_cfg_init(void); 326 #endif /* IMAGE_BL2 */ 327 328 #if MEASURED_BOOT 329 #if DICE_PROTECTION_ENVIRONMENT 330 int arm_set_nt_fw_info(int *ctx_handle); 331 int arm_set_tb_fw_info(int *ctx_handle); 332 int arm_get_tb_fw_info(int *ctx_handle); 333 #else 334 /* Specific to event log backend */ 335 int arm_set_tos_fw_info(uintptr_t log_addr, size_t log_size); 336 int arm_set_nt_fw_info( 337 /* 338 * Currently OP-TEE does not support reading DTBs from Secure memory 339 * and this option should be removed when feature is supported. 340 */ 341 #ifdef SPD_opteed 342 uintptr_t log_addr, 343 #endif 344 size_t log_size, uintptr_t *ns_log_addr); 345 int arm_set_tb_fw_info(uintptr_t log_addr, size_t log_size, 346 size_t log_max_size); 347 int arm_get_tb_fw_info(uint64_t *log_addr, size_t *log_size, 348 size_t *log_max_size); 349 #endif /* DICE_PROTECTION_ENVIRONMENT */ 350 #endif /* MEASURED_BOOT */ 351 352 /* 353 * Free the memory storing initialization code only used during an images boot 354 * time so it can be reclaimed for runtime data 355 */ 356 void arm_free_init_memory(void); 357 358 /* 359 * Make the higher level translation tables read-only 360 */ 361 void arm_xlat_make_tables_readonly(void); 362 363 /* 364 * Mandatory functions required in ARM standard platforms 365 */ 366 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 367 368 /* should not be used, but keep for compatibility */ 369 #if USE_GIC_DRIVER == 0 370 void plat_arm_gic_driver_init(void); 371 void plat_arm_gic_init(void); 372 void plat_arm_gic_cpuif_enable(void); 373 void plat_arm_gic_cpuif_disable(void); 374 void plat_arm_gic_redistif_on(void); 375 void plat_arm_gic_redistif_off(void); 376 void plat_arm_gic_pcpu_init(void); 377 void plat_arm_gic_save(void); 378 void plat_arm_gic_resume(void); 379 #endif 380 void plat_arm_security_setup(void); 381 void plat_arm_pwrc_setup(void); 382 void plat_arm_interconnect_init(void); 383 void plat_arm_interconnect_enter_coherency(void); 384 void plat_arm_interconnect_exit_coherency(void); 385 void plat_arm_program_trusted_mailbox(uintptr_t address); 386 bool plat_arm_bl1_fwu_needed(void); 387 int plat_arm_ni_setup(uintptr_t global_cfg); 388 __dead2 void plat_arm_error_handler(int err); 389 __dead2 void plat_arm_system_reset(void); 390 391 /* 392 * Optional functions in ARM standard platforms 393 */ 394 void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames); 395 int arm_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len, 396 unsigned int *flags); 397 int arm_get_rotpk_info_regs(void **key_ptr, unsigned int *key_len, 398 unsigned int *flags); 399 int arm_get_rotpk_info_cc(void **key_ptr, unsigned int *key_len, 400 unsigned int *flags); 401 int arm_get_rotpk_info_dev(void **key_ptr, unsigned int *key_len, 402 unsigned int *flags); 403 404 #if ARM_PLAT_MT 405 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 406 #endif 407 408 unsigned int plat_cluster_id_by_mpidr(u_register_t mpidr); 409 410 /* 411 * This function is called after loading SCP_BL2 image and it is used to perform 412 * any platform-specific actions required to handle the SCP firmware. 413 */ 414 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 415 416 /* 417 * Optional functions required in ARM standard platforms 418 */ 419 void plat_arm_io_setup(void); 420 int plat_arm_get_alt_image_source( 421 unsigned int image_id, 422 uintptr_t *dev_handle, 423 uintptr_t *image_spec); 424 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 425 const mmap_region_t *plat_arm_get_mmap(void); 426 427 const arm_gpt_info_t *plat_arm_get_gpt_info(void); 428 void arm_gpt_setup(void); 429 430 /* Allow platform to override psci_pm_ops during runtime */ 431 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 432 433 /* Execution state switch in ARM platforms */ 434 int arm_execution_state_switch(unsigned int smc_fid, 435 uint32_t pc_hi, 436 uint32_t pc_lo, 437 uint32_t cookie_hi, 438 uint32_t cookie_lo, 439 void *handle); 440 441 /* Optional functions for SP_MIN */ 442 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 443 u_register_t arg2, u_register_t arg3); 444 445 /* global variables */ 446 extern plat_psci_ops_t plat_arm_psci_pm_ops; 447 extern const mmap_region_t plat_arm_mmap[]; 448 extern const unsigned int arm_pm_idle_states[]; 449 extern struct transfer_list_header *secure_tl; 450 451 /* secure watchdog */ 452 void plat_arm_secure_wdt_start(void); 453 void plat_arm_secure_wdt_stop(void); 454 void plat_arm_secure_wdt_refresh(void); 455 456 /* Get SOC-ID of ARM platform */ 457 uint32_t plat_arm_get_soc_id(void); 458 459 #endif /* PLAT_ARM_H */ 460