1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __PLAT_ARM_H__ 7 #define __PLAT_ARM_H__ 8 9 #include <arm_xlat_tables.h> 10 #include <bakery_lock.h> 11 #include <cassert.h> 12 #include <cpu_data.h> 13 #include <stdint.h> 14 #include <tzc_common.h> 15 #include <utils_def.h> 16 17 /******************************************************************************* 18 * Forward declarations 19 ******************************************************************************/ 20 struct meminfo; 21 struct image_info; 22 struct bl_params; 23 24 typedef struct arm_tzc_regions_info { 25 unsigned long long base; 26 unsigned long long end; 27 tzc_region_attributes_t sec_attr; 28 unsigned int nsaid_permissions; 29 } arm_tzc_regions_info_t; 30 31 /******************************************************************************* 32 * Default mapping definition of the TrustZone Controller for ARM standard 33 * platforms. 34 * Configure: 35 * - Region 0 with no access; 36 * - Region 1 with secure access only; 37 * - the remaining DRAM regions access from the given Non-Secure masters. 38 ******************************************************************************/ 39 #if ENABLE_SPM 40 #define ARM_TZC_REGIONS_DEF \ 41 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 42 TZC_REGION_S_RDWR, 0}, \ 43 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 44 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 45 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 46 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 47 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ 48 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 49 PLAT_ARM_TZC_NS_DEV_ACCESS} 50 51 #else 52 #define ARM_TZC_REGIONS_DEF \ 53 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 54 TZC_REGION_S_RDWR, 0}, \ 55 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 56 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 57 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 58 PLAT_ARM_TZC_NS_DEV_ACCESS} 59 #endif 60 61 #define ARM_CASSERT_MMAP \ 62 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 63 assert_plat_arm_mmap_mismatch); \ 64 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 65 <= MAX_MMAP_REGIONS, \ 66 assert_max_mmap_regions); 67 68 /* 69 * Utility functions common to ARM standard platforms 70 */ 71 void arm_setup_page_tables(const mmap_region_t bl_regions[], 72 const mmap_region_t plat_regions[]); 73 74 void arm_setup_romlib(void); 75 76 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) 77 /* 78 * Use this macro to instantiate lock before it is used in below 79 * arm_lock_xxx() macros 80 */ 81 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 82 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 83 /* 84 * These are wrapper macros to the Coherent Memory Bakery Lock API. 85 */ 86 #define arm_lock_init() bakery_lock_init(&arm_lock) 87 #define arm_lock_get() bakery_lock_get(&arm_lock) 88 #define arm_lock_release() bakery_lock_release(&arm_lock) 89 90 #else 91 92 /* 93 * Empty macros for all other BL stages other than BL31 and BL32 94 */ 95 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 96 #define ARM_LOCK_GET_INSTANCE 0 97 #define arm_lock_init() 98 #define arm_lock_get() 99 #define arm_lock_release() 100 101 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ 102 103 #if ARM_RECOM_STATE_ID_ENC 104 /* 105 * Macros used to parse state information from State-ID if it is using the 106 * recommended encoding for State-ID. 107 */ 108 #define ARM_LOCAL_PSTATE_WIDTH 4 109 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 110 111 /* Macros to construct the composite power state */ 112 113 /* Make composite power state parameter till power level 0 */ 114 #if PSCI_EXTENDED_STATE_ID 115 116 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 117 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 118 #else 119 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 120 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 121 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 122 ((type) << PSTATE_TYPE_SHIFT)) 123 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 124 125 /* Make composite power state parameter till power level 1 */ 126 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 127 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 128 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 129 130 /* Make composite power state parameter till power level 2 */ 131 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 132 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 133 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 134 135 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 136 137 /* ARM State switch error codes */ 138 #define STATE_SW_E_PARAM (-2) 139 #define STATE_SW_E_DENIED (-3) 140 141 /* IO storage utility functions */ 142 void arm_io_setup(void); 143 144 /* Security utility functions */ 145 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); 146 struct tzc_dmc500_driver_data; 147 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 148 const arm_tzc_regions_info_t *tzc_regions); 149 150 /* Console utility functions */ 151 void arm_console_boot_init(void); 152 void arm_console_boot_end(void); 153 void arm_console_runtime_init(void); 154 void arm_console_runtime_end(void); 155 156 /* Systimer utility function */ 157 void arm_configure_sys_timer(void); 158 159 /* PM utility functions */ 160 int arm_validate_power_state(unsigned int power_state, 161 psci_power_state_t *req_state); 162 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 163 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 164 void arm_system_pwr_domain_save(void); 165 void arm_system_pwr_domain_resume(void); 166 int arm_psci_read_mem_protect(int *enabled); 167 int arm_nor_psci_write_mem_protect(int val); 168 void arm_nor_psci_do_static_mem_protect(void); 169 void arm_nor_psci_do_dyn_mem_protect(void); 170 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 171 172 /* Topology utility function */ 173 int arm_check_mpidr(u_register_t mpidr); 174 175 /* BL1 utility functions */ 176 void arm_bl1_early_platform_setup(void); 177 void arm_bl1_platform_setup(void); 178 void arm_bl1_plat_arch_setup(void); 179 180 /* BL2 utility functions */ 181 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 182 void arm_bl2_platform_setup(void); 183 void arm_bl2_plat_arch_setup(void); 184 uint32_t arm_get_spsr_for_bl32_entry(void); 185 uint32_t arm_get_spsr_for_bl33_entry(void); 186 int arm_bl2_handle_post_image_load(unsigned int image_id); 187 188 /* BL2 at EL3 functions */ 189 void arm_bl2_el3_early_platform_setup(void); 190 void arm_bl2_el3_plat_arch_setup(void); 191 192 /* BL2U utility functions */ 193 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 194 void *plat_info); 195 void arm_bl2u_platform_setup(void); 196 void arm_bl2u_plat_arch_setup(void); 197 198 /* BL31 utility functions */ 199 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 200 uintptr_t hw_config, void *plat_params_from_bl2); 201 void arm_bl31_platform_setup(void); 202 void arm_bl31_plat_runtime_setup(void); 203 void arm_bl31_plat_arch_setup(void); 204 205 /* TSP utility functions */ 206 void arm_tsp_early_platform_setup(void); 207 208 /* SP_MIN utility functions */ 209 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 210 uintptr_t hw_config, void *plat_params_from_bl2); 211 void arm_sp_min_plat_runtime_setup(void); 212 213 /* FIP TOC validity check */ 214 int arm_io_is_toc_valid(void); 215 216 /* Utility functions for Dynamic Config */ 217 void arm_load_tb_fw_config(void); 218 void arm_bl2_set_tb_cfg_addr(void *dtb); 219 void arm_bl2_dyn_cfg_init(void); 220 void arm_bl1_set_mbedtls_heap(void); 221 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 222 223 /* 224 * Mandatory functions required in ARM standard platforms 225 */ 226 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 227 void plat_arm_gic_driver_init(void); 228 void plat_arm_gic_init(void); 229 void plat_arm_gic_cpuif_enable(void); 230 void plat_arm_gic_cpuif_disable(void); 231 void plat_arm_gic_redistif_on(void); 232 void plat_arm_gic_redistif_off(void); 233 void plat_arm_gic_pcpu_init(void); 234 void plat_arm_gic_save(void); 235 void plat_arm_gic_resume(void); 236 void plat_arm_security_setup(void); 237 void plat_arm_pwrc_setup(void); 238 void plat_arm_interconnect_init(void); 239 void plat_arm_interconnect_enter_coherency(void); 240 void plat_arm_interconnect_exit_coherency(void); 241 void plat_arm_program_trusted_mailbox(uintptr_t address); 242 int plat_arm_bl1_fwu_needed(void); 243 void plat_arm_error_handler(int err); 244 245 #if ARM_PLAT_MT 246 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 247 #endif 248 249 /* 250 * This function is called after loading SCP_BL2 image and it is used to perform 251 * any platform-specific actions required to handle the SCP firmware. 252 */ 253 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 254 255 /* 256 * Optional functions required in ARM standard platforms 257 */ 258 void plat_arm_io_setup(void); 259 int plat_arm_get_alt_image_source( 260 unsigned int image_id, 261 uintptr_t *dev_handle, 262 uintptr_t *image_spec); 263 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 264 const mmap_region_t *plat_arm_get_mmap(void); 265 266 /* Allow platform to override psci_pm_ops during runtime */ 267 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 268 269 /* Execution state switch in ARM platforms */ 270 int arm_execution_state_switch(unsigned int smc_fid, 271 uint32_t pc_hi, 272 uint32_t pc_lo, 273 uint32_t cookie_hi, 274 uint32_t cookie_lo, 275 void *handle); 276 277 /* Optional functions for SP_MIN */ 278 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 279 u_register_t arg2, u_register_t arg3); 280 281 /* global variables */ 282 extern plat_psci_ops_t plat_arm_psci_pm_ops; 283 extern const mmap_region_t plat_arm_mmap[]; 284 extern const unsigned int arm_pm_idle_states[]; 285 286 #endif /* __PLAT_ARM_H__ */ 287