1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __PLAT_ARM_H__ 7 #define __PLAT_ARM_H__ 8 9 #include <arm_xlat_tables.h> 10 #include <bakery_lock.h> 11 #include <cassert.h> 12 #include <cpu_data.h> 13 #include <stdint.h> 14 #include <spinlock.h> 15 #include <tzc_common.h> 16 #include <utils_def.h> 17 18 /******************************************************************************* 19 * Forward declarations 20 ******************************************************************************/ 21 struct meminfo; 22 struct image_info; 23 struct bl_params; 24 25 typedef struct arm_tzc_regions_info { 26 unsigned long long base; 27 unsigned long long end; 28 unsigned int sec_attr; 29 unsigned int nsaid_permissions; 30 } arm_tzc_regions_info_t; 31 32 /******************************************************************************* 33 * Default mapping definition of the TrustZone Controller for ARM standard 34 * platforms. 35 * Configure: 36 * - Region 0 with no access; 37 * - Region 1 with secure access only; 38 * - the remaining DRAM regions access from the given Non-Secure masters. 39 ******************************************************************************/ 40 #if ENABLE_SPM 41 #define ARM_TZC_REGIONS_DEF \ 42 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 43 TZC_REGION_S_RDWR, 0}, \ 44 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 45 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 46 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 47 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 48 {ARM_SP_IMAGE_NS_BUF_BASE, (ARM_SP_IMAGE_NS_BUF_BASE + \ 49 ARM_SP_IMAGE_NS_BUF_SIZE) - 1, TZC_REGION_S_NONE, \ 50 PLAT_ARM_TZC_NS_DEV_ACCESS} 51 52 #else 53 #define ARM_TZC_REGIONS_DEF \ 54 {ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END, \ 55 TZC_REGION_S_RDWR, 0}, \ 56 {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 57 PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 58 {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 59 PLAT_ARM_TZC_NS_DEV_ACCESS} 60 #endif 61 62 #define ARM_CASSERT_MMAP \ 63 CASSERT((ARRAY_SIZE(plat_arm_mmap) - 1) <= PLAT_ARM_MMAP_ENTRIES, \ 64 assert_plat_arm_mmap_mismatch); \ 65 CASSERT((PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS) \ 66 <= MAX_MMAP_REGIONS, \ 67 assert_max_mmap_regions); 68 69 /* 70 * Utility functions common to ARM standard platforms 71 */ 72 void arm_setup_page_tables(const mmap_region_t bl_regions[], 73 const mmap_region_t plat_regions[]); 74 75 void arm_setup_romlib(void); 76 77 #if defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) 78 /* 79 * Use this macro to instantiate lock before it is used in below 80 * arm_lock_xxx() macros 81 */ 82 #define ARM_INSTANTIATE_LOCK static DEFINE_BAKERY_LOCK(arm_lock) 83 #define ARM_LOCK_GET_INSTANCE (&arm_lock) 84 85 #if !HW_ASSISTED_COHERENCY 86 #define ARM_SCMI_INSTANTIATE_LOCK DEFINE_BAKERY_LOCK(arm_scmi_lock) 87 #else 88 #define ARM_SCMI_INSTANTIATE_LOCK spinlock_t arm_scmi_lock 89 #endif 90 #define ARM_SCMI_LOCK_GET_INSTANCE (&arm_scmi_lock) 91 92 /* 93 * These are wrapper macros to the Coherent Memory Bakery Lock API. 94 */ 95 #define arm_lock_init() bakery_lock_init(&arm_lock) 96 #define arm_lock_get() bakery_lock_get(&arm_lock) 97 #define arm_lock_release() bakery_lock_release(&arm_lock) 98 99 #else 100 101 /* 102 * Empty macros for all other BL stages other than BL31 and BL32 103 */ 104 #define ARM_INSTANTIATE_LOCK static int arm_lock __unused 105 #define ARM_LOCK_GET_INSTANCE 0 106 #define arm_lock_init() 107 #define arm_lock_get() 108 #define arm_lock_release() 109 110 #endif /* defined(IMAGE_BL31) || (defined(AARCH32) && defined(IMAGE_BL32)) */ 111 112 #if ARM_RECOM_STATE_ID_ENC 113 /* 114 * Macros used to parse state information from State-ID if it is using the 115 * recommended encoding for State-ID. 116 */ 117 #define ARM_LOCAL_PSTATE_WIDTH 4 118 #define ARM_LOCAL_PSTATE_MASK ((1 << ARM_LOCAL_PSTATE_WIDTH) - 1) 119 120 /* Macros to construct the composite power state */ 121 122 /* Make composite power state parameter till power level 0 */ 123 #if PSCI_EXTENDED_STATE_ID 124 125 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 126 (((lvl0_state) << PSTATE_ID_SHIFT) | ((type) << PSTATE_TYPE_SHIFT)) 127 #else 128 #define arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \ 129 (((lvl0_state) << PSTATE_ID_SHIFT) | \ 130 ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \ 131 ((type) << PSTATE_TYPE_SHIFT)) 132 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 133 134 /* Make composite power state parameter till power level 1 */ 135 #define arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \ 136 (((lvl1_state) << ARM_LOCAL_PSTATE_WIDTH) | \ 137 arm_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type)) 138 139 /* Make composite power state parameter till power level 2 */ 140 #define arm_make_pwrstate_lvl2(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \ 141 (((lvl2_state) << (ARM_LOCAL_PSTATE_WIDTH * 2)) | \ 142 arm_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type)) 143 144 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 145 146 /* ARM State switch error codes */ 147 #define STATE_SW_E_PARAM (-2) 148 #define STATE_SW_E_DENIED (-3) 149 150 /* IO storage utility functions */ 151 void arm_io_setup(void); 152 153 /* Security utility functions */ 154 void arm_tzc400_setup(const arm_tzc_regions_info_t *tzc_regions); 155 struct tzc_dmc500_driver_data; 156 void arm_tzc_dmc500_setup(struct tzc_dmc500_driver_data *plat_driver_data, 157 const arm_tzc_regions_info_t *tzc_regions); 158 159 /* Console utility functions */ 160 void arm_console_boot_init(void); 161 void arm_console_boot_end(void); 162 void arm_console_runtime_init(void); 163 void arm_console_runtime_end(void); 164 165 /* Systimer utility function */ 166 void arm_configure_sys_timer(void); 167 168 /* PM utility functions */ 169 int arm_validate_power_state(unsigned int power_state, 170 psci_power_state_t *req_state); 171 int arm_validate_psci_entrypoint(uintptr_t entrypoint); 172 int arm_validate_ns_entrypoint(uintptr_t entrypoint); 173 void arm_system_pwr_domain_save(void); 174 void arm_system_pwr_domain_resume(void); 175 int arm_psci_read_mem_protect(int *enabled); 176 int arm_nor_psci_write_mem_protect(int val); 177 void arm_nor_psci_do_static_mem_protect(void); 178 void arm_nor_psci_do_dyn_mem_protect(void); 179 int arm_psci_mem_protect_chk(uintptr_t base, u_register_t length); 180 181 /* Topology utility function */ 182 int arm_check_mpidr(u_register_t mpidr); 183 184 /* BL1 utility functions */ 185 void arm_bl1_early_platform_setup(void); 186 void arm_bl1_platform_setup(void); 187 void arm_bl1_plat_arch_setup(void); 188 189 /* BL2 utility functions */ 190 void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); 191 void arm_bl2_platform_setup(void); 192 void arm_bl2_plat_arch_setup(void); 193 uint32_t arm_get_spsr_for_bl32_entry(void); 194 uint32_t arm_get_spsr_for_bl33_entry(void); 195 int arm_bl2_handle_post_image_load(unsigned int image_id); 196 197 /* BL2 at EL3 functions */ 198 void arm_bl2_el3_early_platform_setup(void); 199 void arm_bl2_el3_plat_arch_setup(void); 200 201 /* BL2U utility functions */ 202 void arm_bl2u_early_platform_setup(struct meminfo *mem_layout, 203 void *plat_info); 204 void arm_bl2u_platform_setup(void); 205 void arm_bl2u_plat_arch_setup(void); 206 207 /* BL31 utility functions */ 208 void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, 209 uintptr_t hw_config, void *plat_params_from_bl2); 210 void arm_bl31_platform_setup(void); 211 void arm_bl31_plat_runtime_setup(void); 212 void arm_bl31_plat_arch_setup(void); 213 214 /* TSP utility functions */ 215 void arm_tsp_early_platform_setup(void); 216 217 /* SP_MIN utility functions */ 218 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 219 uintptr_t hw_config, void *plat_params_from_bl2); 220 void arm_sp_min_plat_runtime_setup(void); 221 222 /* FIP TOC validity check */ 223 int arm_io_is_toc_valid(void); 224 225 /* Utility functions for Dynamic Config */ 226 void arm_load_tb_fw_config(void); 227 void arm_bl2_set_tb_cfg_addr(void *dtb); 228 void arm_bl2_dyn_cfg_init(void); 229 void arm_bl1_set_mbedtls_heap(void); 230 int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size); 231 232 /* 233 * Free the memory storing initialization code only used during an images boot 234 * time so it can be reclaimed for runtime data 235 */ 236 void arm_free_init_memory(void); 237 238 /* 239 * Mandatory functions required in ARM standard platforms 240 */ 241 unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr); 242 void plat_arm_gic_driver_init(void); 243 void plat_arm_gic_init(void); 244 void plat_arm_gic_cpuif_enable(void); 245 void plat_arm_gic_cpuif_disable(void); 246 void plat_arm_gic_redistif_on(void); 247 void plat_arm_gic_redistif_off(void); 248 void plat_arm_gic_pcpu_init(void); 249 void plat_arm_gic_save(void); 250 void plat_arm_gic_resume(void); 251 void plat_arm_security_setup(void); 252 void plat_arm_pwrc_setup(void); 253 void plat_arm_interconnect_init(void); 254 void plat_arm_interconnect_enter_coherency(void); 255 void plat_arm_interconnect_exit_coherency(void); 256 void plat_arm_program_trusted_mailbox(uintptr_t address); 257 int plat_arm_bl1_fwu_needed(void); 258 void plat_arm_error_handler(int err); 259 260 #if ARM_PLAT_MT 261 unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr); 262 #endif 263 264 /* 265 * This function is called after loading SCP_BL2 image and it is used to perform 266 * any platform-specific actions required to handle the SCP firmware. 267 */ 268 int plat_arm_bl2_handle_scp_bl2(struct image_info *scp_bl2_image_info); 269 270 /* 271 * Optional functions required in ARM standard platforms 272 */ 273 void plat_arm_io_setup(void); 274 int plat_arm_get_alt_image_source( 275 unsigned int image_id, 276 uintptr_t *dev_handle, 277 uintptr_t *image_spec); 278 unsigned int plat_arm_calc_core_pos(u_register_t mpidr); 279 const mmap_region_t *plat_arm_get_mmap(void); 280 281 /* Allow platform to override psci_pm_ops during runtime */ 282 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops); 283 284 /* Execution state switch in ARM platforms */ 285 int arm_execution_state_switch(unsigned int smc_fid, 286 uint32_t pc_hi, 287 uint32_t pc_lo, 288 uint32_t cookie_hi, 289 uint32_t cookie_lo, 290 void *handle); 291 292 /* Optional functions for SP_MIN */ 293 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 294 u_register_t arg2, u_register_t arg3); 295 296 /* global variables */ 297 extern plat_psci_ops_t plat_arm_psci_pm_ops; 298 extern const mmap_region_t plat_arm_mmap[]; 299 extern const unsigned int arm_pm_idle_states[]; 300 301 #endif /* __PLAT_ARM_H__ */ 302