xref: /rk3399_ARM-atf/include/plat/arm/common/arm_tzc_dram.ld.S (revision cb4adb0d8c36e6650b8b74d27e8c7417067e8cd5)
1*cb4adb0dSDaniel Boulby/*
2*cb4adb0dSDaniel Boulby * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3*cb4adb0dSDaniel Boulby *
4*cb4adb0dSDaniel Boulby * SPDX-License-Identifier: BSD-3-Clause
5*cb4adb0dSDaniel Boulby */
6*cb4adb0dSDaniel Boulby#ifndef ARM_TZC_DRAM_LD_S__
7*cb4adb0dSDaniel Boulby#define ARM_TZC_DRAM_LD_S__
8*cb4adb0dSDaniel Boulby
9*cb4adb0dSDaniel Boulby#include <xlat_tables_defs.h>
10*cb4adb0dSDaniel Boulby
11*cb4adb0dSDaniel BoulbyMEMORY {
12*cb4adb0dSDaniel Boulby    EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE
13*cb4adb0dSDaniel Boulby}
14*cb4adb0dSDaniel Boulby
15*cb4adb0dSDaniel BoulbySECTIONS
16*cb4adb0dSDaniel Boulby{
17*cb4adb0dSDaniel Boulby	. = ARM_EL3_TZC_DRAM1_BASE;
18*cb4adb0dSDaniel Boulby	ASSERT(. == ALIGN(PAGE_SIZE),
19*cb4adb0dSDaniel Boulby	"ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.")
20*cb4adb0dSDaniel Boulby	el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) {
21*cb4adb0dSDaniel Boulby	__EL3_SEC_DRAM_START__ = .;
22*cb4adb0dSDaniel Boulby	*(arm_el3_tzc_dram)
23*cb4adb0dSDaniel Boulby	__EL3_SEC_DRAM_UNALIGNED_END__ = .;
24*cb4adb0dSDaniel Boulby
25*cb4adb0dSDaniel Boulby	. = ALIGN(PAGE_SIZE);
26*cb4adb0dSDaniel Boulby	__EL3_SEC_DRAM_END__ = .;
27*cb4adb0dSDaniel Boulby	} >EL3_SEC_DRAM
28*cb4adb0dSDaniel Boulby}
29*cb4adb0dSDaniel Boulby
30*cb4adb0dSDaniel Boulby#endif /* ARM_TZC_DRAM_LD_S__ */
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