1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_SPM_DEF_H 7 #define ARM_SPM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_defs.h> 11 12 /* 13 * Reserve 4 MiB for binaries of Secure Partitions and Resource Description 14 * blobs. 15 */ 16 #define PLAT_SP_PACKAGE_BASE BL32_BASE 17 #define PLAT_SP_PACKAGE_SIZE ULL(0x400000) 18 19 #define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \ 20 PLAT_SP_PACKAGE_BASE, \ 21 PLAT_SP_PACKAGE_SIZE, \ 22 MT_MEMORY | MT_RO | MT_SECURE) 23 #define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \ 24 PLAT_SP_PACKAGE_BASE, \ 25 PLAT_SP_PACKAGE_SIZE, \ 26 MT_MEMORY | MT_RW | MT_SECURE) 27 28 /* 29 * The rest of the memory reserved for BL32 is free for SPM to use it as memory 30 * pool to allocate memory regions requested in the resource description. 31 */ 32 #define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE) 33 #define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE) 34 35 #if SPM_DEPRECATED 36 37 /* 38 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 39 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 40 * at the base of DRAM. 41 */ 42 #define ARM_SP_IMAGE_BASE BL32_BASE 43 #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 44 /* The maximum size of the S-EL0 payload can be 3MB */ 45 #define ARM_SP_IMAGE_SIZE ULL(0x300000) 46 47 #ifdef IMAGE_BL2 48 /* SPM Payload memory. Mapped as RW in BL2. */ 49 #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 50 ARM_SP_IMAGE_BASE, \ 51 ARM_SP_IMAGE_SIZE, \ 52 MT_MEMORY | MT_RW | MT_SECURE) 53 #endif 54 55 #ifdef IMAGE_BL31 56 /* SPM Payload memory. Mapped as code in S-EL1 */ 57 #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 58 ARM_SP_IMAGE_BASE, \ 59 ARM_SP_IMAGE_BASE, \ 60 ARM_SP_IMAGE_SIZE, \ 61 MT_CODE | MT_SECURE | MT_USER, \ 62 PAGE_SIZE) 63 #endif 64 65 /* 66 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 67 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 68 * from S-EL0. Placed after SPM Payload memory. 69 */ 70 #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 71 #define PLAT_SPM_BUF_SIZE ULL(0x100000) 72 73 #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 74 PLAT_SPM_BUF_BASE, \ 75 PLAT_SPM_BUF_SIZE, \ 76 MT_RW_DATA | MT_SECURE) 77 #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 78 PLAT_SPM_BUF_BASE, \ 79 PLAT_SPM_BUF_BASE, \ 80 PLAT_SPM_BUF_SIZE, \ 81 MT_RO_DATA | MT_SECURE | MT_USER,\ 82 PAGE_SIZE) 83 84 /* 85 * Memory shared between Normal world and S-EL0 for passing data during service 86 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 87 * S-EL0. 88 */ 89 #define PLAT_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) 90 #define PLAT_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 91 #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 92 PLAT_SP_IMAGE_NS_BUF_BASE, \ 93 PLAT_SP_IMAGE_NS_BUF_BASE, \ 94 PLAT_SP_IMAGE_NS_BUF_SIZE, \ 95 MT_RW_DATA | MT_NS | MT_USER, \ 96 PAGE_SIZE) 97 98 /* 99 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 100 * shared between Secure and Non-secure worlds, or after the platform specific 101 * buffers, if defined. First there is the stack memory for all CPUs and then 102 * there is the common heap memory. Both are mapped with RW permissions. 103 */ 104 #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 105 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 106 #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 107 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 108 109 #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 110 ARM_SP_IMAGE_STACK_TOTAL_SIZE) 111 #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) 112 113 #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 114 PLAT_SP_IMAGE_STACK_BASE, \ 115 PLAT_SP_IMAGE_STACK_BASE, \ 116 (ARM_SP_IMAGE_LIMIT - \ 117 PLAT_SP_IMAGE_STACK_BASE), \ 118 MT_RW_DATA | MT_SECURE | MT_USER,\ 119 PAGE_SIZE) 120 121 /* Total number of memory regions with distinct properties */ 122 #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 123 124 #endif /* SPM_DEPRECATED */ 125 126 /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 127 #define PLAT_SPM_COOKIE_0 ULL(0) 128 #define PLAT_SPM_COOKIE_1 ULL(0) 129 130 /* 131 * Max number of elements supported by SPM in this platform. The defines below 132 * are used to allocate memory at compile time for different arrays in SPM. 133 */ 134 #define PLAT_SPM_MAX_PARTITIONS U(2) 135 136 #define PLAT_SPM_MEM_REGIONS_MAX U(80) 137 #define PLAT_SPM_NOTIFICATIONS_MAX U(30) 138 #define PLAT_SPM_SERVICES_MAX U(30) 139 140 #define PLAT_SPCI_HANDLES_MAX_NUM U(20) 141 #define PLAT_SPM_RESPONSES_MAX U(30) 142 143 #endif /* ARM_SPM_DEF_H */ 144