1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_SPM_DEF_H 7 #define ARM_SPM_DEF_H 8 9 #include <arm_def.h> 10 #include <utils_def.h> 11 #include <xlat_tables_defs.h> 12 13 /* 14 * Reserve 4 MiB for binaries of Secure Partitions and Resource Description 15 * blobs. 16 */ 17 #define PLAT_SP_PACKAGE_BASE BL32_BASE 18 #define PLAT_SP_PACKAGE_SIZE ULL(0x400000) 19 20 #define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \ 21 PLAT_SP_PACKAGE_BASE, \ 22 PLAT_SP_PACKAGE_SIZE, \ 23 MT_MEMORY | MT_RO | MT_SECURE) 24 #define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \ 25 PLAT_SP_PACKAGE_BASE, \ 26 PLAT_SP_PACKAGE_SIZE, \ 27 MT_MEMORY | MT_RW | MT_SECURE) 28 29 /* 30 * The rest of the memory reserved for BL32 is free for SPM to use it as memory 31 * pool to allocate memory regions requested in the resource description. 32 */ 33 #define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE) 34 #define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE) 35 36 #if SPM_DEPRECATED 37 38 /* 39 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 40 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 41 * at the base of DRAM. 42 */ 43 #define ARM_SP_IMAGE_BASE BL32_BASE 44 #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 45 /* The maximum size of the S-EL0 payload can be 3MB */ 46 #define ARM_SP_IMAGE_SIZE ULL(0x300000) 47 48 #ifdef IMAGE_BL2 49 /* SPM Payload memory. Mapped as RW in BL2. */ 50 #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 51 ARM_SP_IMAGE_BASE, \ 52 ARM_SP_IMAGE_SIZE, \ 53 MT_MEMORY | MT_RW | MT_SECURE) 54 #endif 55 56 #ifdef IMAGE_BL31 57 /* SPM Payload memory. Mapped as code in S-EL1 */ 58 #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 59 ARM_SP_IMAGE_BASE, \ 60 ARM_SP_IMAGE_BASE, \ 61 ARM_SP_IMAGE_SIZE, \ 62 MT_CODE | MT_SECURE | MT_USER, \ 63 PAGE_SIZE) 64 #endif 65 66 /* 67 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 68 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 69 * from S-EL0. Placed after SPM Payload memory. 70 */ 71 #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 72 #define PLAT_SPM_BUF_SIZE ULL(0x100000) 73 74 #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 75 PLAT_SPM_BUF_BASE, \ 76 PLAT_SPM_BUF_SIZE, \ 77 MT_RW_DATA | MT_SECURE) 78 #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 79 PLAT_SPM_BUF_BASE, \ 80 PLAT_SPM_BUF_BASE, \ 81 PLAT_SPM_BUF_SIZE, \ 82 MT_RO_DATA | MT_SECURE | MT_USER,\ 83 PAGE_SIZE) 84 85 /* 86 * Memory shared between Normal world and S-EL0 for passing data during service 87 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 88 * S-EL0. 89 */ 90 #define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) 91 #define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 92 #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 93 ARM_SP_IMAGE_NS_BUF_BASE, \ 94 ARM_SP_IMAGE_NS_BUF_BASE, \ 95 ARM_SP_IMAGE_NS_BUF_SIZE, \ 96 MT_RW_DATA | MT_NS | MT_USER, \ 97 PAGE_SIZE) 98 99 /* 100 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 101 * shared between Secure and Non-secure worlds, or after the platform specific 102 * buffers, if defined. First there is the stack memory for all CPUs and then 103 * there is the common heap memory. Both are mapped with RW permissions. 104 */ 105 #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 106 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 107 #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 108 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 109 110 #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 111 ARM_SP_IMAGE_STACK_TOTAL_SIZE) 112 #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) 113 114 #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 115 PLAT_SP_IMAGE_STACK_BASE, \ 116 PLAT_SP_IMAGE_STACK_BASE, \ 117 (ARM_SP_IMAGE_LIMIT - \ 118 PLAT_SP_IMAGE_STACK_BASE), \ 119 MT_RW_DATA | MT_SECURE | MT_USER,\ 120 PAGE_SIZE) 121 122 /* Total number of memory regions with distinct properties */ 123 #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 124 125 #endif /* SPM_DEPRECATED */ 126 127 /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 128 #define PLAT_SPM_COOKIE_0 ULL(0) 129 #define PLAT_SPM_COOKIE_1 ULL(0) 130 131 /* 132 * Max number of elements supported by SPM in this platform. The defines below 133 * are used to allocate memory at compile time for different arrays in SPM. 134 */ 135 #define PLAT_SPM_MAX_PARTITIONS U(2) 136 137 #define PLAT_SPM_MEM_REGIONS_MAX U(80) 138 #define PLAT_SPM_NOTIFICATIONS_MAX U(30) 139 #define PLAT_SPM_SERVICES_MAX U(30) 140 141 #define PLAT_SPCI_HANDLES_MAX_NUM U(20) 142 143 #endif /* ARM_SPM_DEF_H */ 144