1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_SPM_DEF_H 7 #define ARM_SPM_DEF_H 8 9 #include <arm_def.h> 10 #include <utils_def.h> 11 #include <xlat_tables_defs.h> 12 13 /* 14 * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 15 * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 16 * at the base of DRAM. 17 */ 18 #define ARM_SP_IMAGE_BASE BL32_BASE 19 #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 20 /* The maximum size of the S-EL0 payload can be 3MB */ 21 #define ARM_SP_IMAGE_SIZE ULL(0x300000) 22 23 #ifdef IMAGE_BL2 24 /* SPM Payload memory. Mapped as RW in BL2. */ 25 #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 26 ARM_SP_IMAGE_BASE, \ 27 ARM_SP_IMAGE_SIZE, \ 28 MT_MEMORY | MT_RW | MT_SECURE) 29 #endif 30 31 #if SPM_DEPRECATED 32 33 #ifdef IMAGE_BL31 34 /* SPM Payload memory. Mapped as code in S-EL1 */ 35 #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 36 ARM_SP_IMAGE_BASE, \ 37 ARM_SP_IMAGE_BASE, \ 38 ARM_SP_IMAGE_SIZE, \ 39 MT_CODE | MT_SECURE | MT_USER, \ 40 PAGE_SIZE) 41 #endif 42 43 /* 44 * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 45 * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 46 * from S-EL0. Placed after SPM Payload memory. 47 */ 48 #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 49 #define PLAT_SPM_BUF_SIZE ULL(0x100000) 50 51 #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 52 PLAT_SPM_BUF_BASE, \ 53 PLAT_SPM_BUF_SIZE, \ 54 MT_RW_DATA | MT_SECURE) 55 #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 56 PLAT_SPM_BUF_BASE, \ 57 PLAT_SPM_BUF_BASE, \ 58 PLAT_SPM_BUF_SIZE, \ 59 MT_RO_DATA | MT_SECURE | MT_USER,\ 60 PAGE_SIZE) 61 62 /* 63 * Memory shared between Normal world and S-EL0 for passing data during service 64 * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 65 * S-EL0. 66 */ 67 #define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) 68 #define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 69 #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 70 ARM_SP_IMAGE_NS_BUF_BASE, \ 71 ARM_SP_IMAGE_NS_BUF_BASE, \ 72 ARM_SP_IMAGE_NS_BUF_SIZE, \ 73 MT_RW_DATA | MT_NS | MT_USER, \ 74 PAGE_SIZE) 75 76 /* 77 * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 78 * shared between Secure and Non-secure worlds, or after the platform specific 79 * buffers, if defined. First there is the stack memory for all CPUs and then 80 * there is the common heap memory. Both are mapped with RW permissions. 81 */ 82 #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 83 #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 84 #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 85 PLAT_SP_IMAGE_STACK_PCPU_SIZE) 86 87 #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 88 ARM_SP_IMAGE_STACK_TOTAL_SIZE) 89 #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) 90 91 #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 92 PLAT_SP_IMAGE_STACK_BASE, \ 93 PLAT_SP_IMAGE_STACK_BASE, \ 94 (ARM_SP_IMAGE_LIMIT - \ 95 PLAT_SP_IMAGE_STACK_BASE), \ 96 MT_RW_DATA | MT_SECURE | MT_USER,\ 97 PAGE_SIZE) 98 99 /* Total number of memory regions with distinct properties */ 100 #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 101 102 #endif /* SPM_DEPRECATED */ 103 104 /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 105 #define PLAT_SPM_COOKIE_0 ULL(0) 106 #define PLAT_SPM_COOKIE_1 ULL(0) 107 108 /* 109 * Max number of elements supported by SPM in this platform. The defines below 110 * are used to allocate memory at compile time for different arrays in SPM. 111 */ 112 #define PLAT_SPM_MEM_REGIONS_MAX U(80) 113 #define PLAT_SPM_NOTIFICATIONS_MAX U(30) 114 #define PLAT_SPM_SERVICES_MAX U(30) 115 116 #endif /* ARM_SPM_DEF_H */ 117