1e29efeb1SAntonio Nino Diaz /* 2e29efeb1SAntonio Nino Diaz * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3e29efeb1SAntonio Nino Diaz * 4e29efeb1SAntonio Nino Diaz * SPDX-License-Identifier: BSD-3-Clause 5e29efeb1SAntonio Nino Diaz */ 6c3cf06f1SAntonio Nino Diaz #ifndef ARM_SPM_DEF_H 7c3cf06f1SAntonio Nino Diaz #define ARM_SPM_DEF_H 8e29efeb1SAntonio Nino Diaz 9e29efeb1SAntonio Nino Diaz #include <arm_def.h> 10e29efeb1SAntonio Nino Diaz #include <utils_def.h> 11e29efeb1SAntonio Nino Diaz #include <xlat_tables_defs.h> 12e29efeb1SAntonio Nino Diaz 13e29efeb1SAntonio Nino Diaz /* 14e29efeb1SAntonio Nino Diaz * If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the 15e29efeb1SAntonio Nino Diaz * region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition 16e29efeb1SAntonio Nino Diaz * at the base of DRAM. 17e29efeb1SAntonio Nino Diaz */ 18e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_BASE BL32_BASE 19e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_LIMIT BL32_LIMIT 20e29efeb1SAntonio Nino Diaz /* The maximum size of the S-EL0 payload can be 3MB */ 21e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_SIZE ULL(0x300000) 22e29efeb1SAntonio Nino Diaz 23e29efeb1SAntonio Nino Diaz #ifdef IMAGE_BL2 24e29efeb1SAntonio Nino Diaz /* SPM Payload memory. Mapped as RW in BL2. */ 25e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_MMAP MAP_REGION_FLAT( \ 26e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_BASE, \ 27e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_SIZE, \ 28e29efeb1SAntonio Nino Diaz MT_MEMORY | MT_RW | MT_SECURE) 29e29efeb1SAntonio Nino Diaz #endif 30*09d413a1SAntonio Nino Diaz 31*09d413a1SAntonio Nino Diaz #if SPM_DEPRECATED 32*09d413a1SAntonio Nino Diaz 33e29efeb1SAntonio Nino Diaz #ifdef IMAGE_BL31 34e29efeb1SAntonio Nino Diaz /* SPM Payload memory. Mapped as code in S-EL1 */ 35e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_MMAP MAP_REGION2( \ 36e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_BASE, \ 37e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_BASE, \ 38e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_SIZE, \ 39e29efeb1SAntonio Nino Diaz MT_CODE | MT_SECURE | MT_USER, \ 40e29efeb1SAntonio Nino Diaz PAGE_SIZE) 41e29efeb1SAntonio Nino Diaz #endif 42e29efeb1SAntonio Nino Diaz 43e29efeb1SAntonio Nino Diaz /* 44e29efeb1SAntonio Nino Diaz * Memory shared between EL3 and S-EL0. It is used by EL3 to push data into 45e29efeb1SAntonio Nino Diaz * S-EL0, so it is mapped with RW permission from EL3 and with RO permission 46e29efeb1SAntonio Nino Diaz * from S-EL0. Placed after SPM Payload memory. 47e29efeb1SAntonio Nino Diaz */ 48e29efeb1SAntonio Nino Diaz #define PLAT_SPM_BUF_BASE (ARM_SP_IMAGE_BASE + ARM_SP_IMAGE_SIZE) 49e29efeb1SAntonio Nino Diaz #define PLAT_SPM_BUF_SIZE ULL(0x100000) 50e29efeb1SAntonio Nino Diaz 51e29efeb1SAntonio Nino Diaz #define ARM_SPM_BUF_EL3_MMAP MAP_REGION_FLAT( \ 52e29efeb1SAntonio Nino Diaz PLAT_SPM_BUF_BASE, \ 53e29efeb1SAntonio Nino Diaz PLAT_SPM_BUF_SIZE, \ 54e29efeb1SAntonio Nino Diaz MT_RW_DATA | MT_SECURE) 55e29efeb1SAntonio Nino Diaz #define ARM_SPM_BUF_EL0_MMAP MAP_REGION2( \ 56e29efeb1SAntonio Nino Diaz PLAT_SPM_BUF_BASE, \ 57e29efeb1SAntonio Nino Diaz PLAT_SPM_BUF_BASE, \ 58e29efeb1SAntonio Nino Diaz PLAT_SPM_BUF_SIZE, \ 59e29efeb1SAntonio Nino Diaz MT_RO_DATA | MT_SECURE | MT_USER,\ 60e29efeb1SAntonio Nino Diaz PAGE_SIZE) 61e29efeb1SAntonio Nino Diaz 62e29efeb1SAntonio Nino Diaz /* 63e29efeb1SAntonio Nino Diaz * Memory shared between Normal world and S-EL0 for passing data during service 64e29efeb1SAntonio Nino Diaz * requests. Mapped as RW and NS. Placed after the shared memory between EL3 and 65e29efeb1SAntonio Nino Diaz * S-EL0. 66e29efeb1SAntonio Nino Diaz */ 67e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_NS_BUF_BASE (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE) 68e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_NS_BUF_SIZE ULL(0x10000) 69e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_NS_BUF_MMAP MAP_REGION2( \ 70e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_NS_BUF_BASE, \ 71e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_NS_BUF_BASE, \ 72e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_NS_BUF_SIZE, \ 73e29efeb1SAntonio Nino Diaz MT_RW_DATA | MT_NS | MT_USER, \ 74e29efeb1SAntonio Nino Diaz PAGE_SIZE) 75e29efeb1SAntonio Nino Diaz 76e29efeb1SAntonio Nino Diaz /* 77e29efeb1SAntonio Nino Diaz * RW memory, which uses the remaining Trusted DRAM. Placed after the memory 782e4a509dSSughosh Ganu * shared between Secure and Non-secure worlds, or after the platform specific 792e4a509dSSughosh Ganu * buffers, if defined. First there is the stack memory for all CPUs and then 802e4a509dSSughosh Ganu * there is the common heap memory. Both are mapped with RW permissions. 81e29efeb1SAntonio Nino Diaz */ 822e4a509dSSughosh Ganu #define PLAT_SP_IMAGE_STACK_BASE PLAT_ARM_SP_IMAGE_STACK_BASE 83e29efeb1SAntonio Nino Diaz #define PLAT_SP_IMAGE_STACK_PCPU_SIZE ULL(0x2000) 84e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_STACK_TOTAL_SIZE (PLATFORM_CORE_COUNT * \ 85e29efeb1SAntonio Nino Diaz PLAT_SP_IMAGE_STACK_PCPU_SIZE) 86e29efeb1SAntonio Nino Diaz 87e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_HEAP_BASE (PLAT_SP_IMAGE_STACK_BASE + \ 88e29efeb1SAntonio Nino Diaz ARM_SP_IMAGE_STACK_TOTAL_SIZE) 89e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_HEAP_SIZE (ARM_SP_IMAGE_LIMIT - ARM_SP_IMAGE_HEAP_BASE) 90e29efeb1SAntonio Nino Diaz 91e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_RW_MMAP MAP_REGION2( \ 92e29efeb1SAntonio Nino Diaz PLAT_SP_IMAGE_STACK_BASE, \ 93e29efeb1SAntonio Nino Diaz PLAT_SP_IMAGE_STACK_BASE, \ 94e29efeb1SAntonio Nino Diaz (ARM_SP_IMAGE_LIMIT - \ 95e29efeb1SAntonio Nino Diaz PLAT_SP_IMAGE_STACK_BASE), \ 96e29efeb1SAntonio Nino Diaz MT_RW_DATA | MT_SECURE | MT_USER,\ 97e29efeb1SAntonio Nino Diaz PAGE_SIZE) 98e29efeb1SAntonio Nino Diaz 99e29efeb1SAntonio Nino Diaz /* Total number of memory regions with distinct properties */ 100e29efeb1SAntonio Nino Diaz #define ARM_SP_IMAGE_NUM_MEM_REGIONS 6 101e29efeb1SAntonio Nino Diaz 102*09d413a1SAntonio Nino Diaz #endif /* SPM_DEPRECATED */ 103*09d413a1SAntonio Nino Diaz 104e29efeb1SAntonio Nino Diaz /* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */ 105e29efeb1SAntonio Nino Diaz #define PLAT_SPM_COOKIE_0 ULL(0) 106e29efeb1SAntonio Nino Diaz #define PLAT_SPM_COOKIE_1 ULL(0) 107e29efeb1SAntonio Nino Diaz 108e458302bSAntonio Nino Diaz /* 109e458302bSAntonio Nino Diaz * Max number of elements supported by SPM in this platform. The defines below 110e458302bSAntonio Nino Diaz * are used to allocate memory at compile time for different arrays in SPM. 111e458302bSAntonio Nino Diaz */ 112e458302bSAntonio Nino Diaz #define PLAT_SPM_MEM_REGIONS_MAX U(80) 113e458302bSAntonio Nino Diaz #define PLAT_SPM_NOTIFICATIONS_MAX U(30) 114e458302bSAntonio Nino Diaz #define PLAT_SPM_SERVICES_MAX U(30) 115e458302bSAntonio Nino Diaz 116c3cf06f1SAntonio Nino Diaz #endif /* ARM_SPM_DEF_H */ 117