1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <platform_def.h> 12 #include <tbbr_img_def.h> 13 #include <utils_def.h> 14 #include <xlat_tables_defs.h> 15 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define ARM_SYSTEM_COUNT 1 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in ARM platforms encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define ARM_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define ARM_LOCAL_STATE_RET 1 44 /* Local power state for OFF/power-down. Valid for CPU and cluster power 45 domains */ 46 #define ARM_LOCAL_STATE_OFF 2 47 48 /* Memory location options for TSP */ 49 #define ARM_TRUSTED_SRAM_ID 0 50 #define ARM_TRUSTED_DRAM_ID 1 51 #define ARM_DRAM_ID 2 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define ARM_TRUSTED_SRAM_BASE 0x04000000 55 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 56 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 57 58 /* The remaining Trusted SRAM is used to load the BL images */ 59 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 60 ARM_SHARED_RAM_SIZE) 61 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 62 ARM_SHARED_RAM_SIZE) 63 64 /* 65 * The top 16MB of DRAM1 is configured as secure access only using the TZC 66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 68 */ 69 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 70 71 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 72 ARM_DRAM1_SIZE - \ 73 ARM_SCP_TZC_DRAM1_SIZE) 74 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 75 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 76 ARM_SCP_TZC_DRAM1_SIZE - 1) 77 78 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 79 ARM_DRAM1_SIZE - \ 80 ARM_TZC_DRAM1_SIZE) 81 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 82 ARM_SCP_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 84 ARM_AP_TZC_DRAM1_SIZE - 1) 85 86 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 87 #if ARM_CRYPTOCELL_INTEG 88 /* 89 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 90 * This is required by CryptoCell to authenticate BL33 which is loaded 91 * into the Non Secure DDR. 92 */ 93 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 94 #else 95 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 96 #endif 97 98 #ifdef SPD_opteed 99 /* 100 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 101 * load/authenticate the trusted os extra image. The first 512KB of 102 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 103 * for OPTEE is paged image which only include the paging part using 104 * virtual memory but without "init" data. OPTEE will copy the "init" data 105 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 106 * extra image behind the "init" data. 107 */ 108 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 109 ARM_AP_TZC_DRAM1_SIZE - \ 110 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 111 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 112 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 113 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 114 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 115 MT_MEMORY | MT_RW | MT_SECURE) 116 117 /* 118 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 119 * support is enabled). 120 */ 121 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 122 BL32_BASE, \ 123 BL32_LIMIT - BL32_BASE, \ 124 MT_MEMORY | MT_RW | MT_SECURE) 125 #endif /* SPD_opteed */ 126 127 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 128 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 129 ARM_TZC_DRAM1_SIZE) 130 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 131 ARM_NS_DRAM1_SIZE - 1) 132 133 #define ARM_DRAM1_BASE ULL(0x80000000) 134 #define ARM_DRAM1_SIZE ULL(0x80000000) 135 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 136 ARM_DRAM1_SIZE - 1) 137 138 #define ARM_DRAM2_BASE ULL(0x880000000) 139 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 140 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 141 ARM_DRAM2_SIZE - 1) 142 143 #define ARM_IRQ_SEC_PHY_TIMER 29 144 145 #define ARM_IRQ_SEC_SGI_0 8 146 #define ARM_IRQ_SEC_SGI_1 9 147 #define ARM_IRQ_SEC_SGI_2 10 148 #define ARM_IRQ_SEC_SGI_3 11 149 #define ARM_IRQ_SEC_SGI_4 12 150 #define ARM_IRQ_SEC_SGI_5 13 151 #define ARM_IRQ_SEC_SGI_6 14 152 #define ARM_IRQ_SEC_SGI_7 15 153 154 /* 155 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 156 * terminology. On a GICv2 system or mode, the lists will be merged and treated 157 * as Group 0 interrupts. 158 */ 159 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 160 ARM_IRQ_SEC_SGI_1, \ 161 ARM_IRQ_SEC_SGI_2, \ 162 ARM_IRQ_SEC_SGI_3, \ 163 ARM_IRQ_SEC_SGI_4, \ 164 ARM_IRQ_SEC_SGI_5, \ 165 ARM_IRQ_SEC_SGI_7 166 167 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 168 ARM_IRQ_SEC_SGI_6 169 170 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 171 ARM_SHARED_RAM_BASE, \ 172 ARM_SHARED_RAM_SIZE, \ 173 MT_DEVICE | MT_RW | MT_SECURE) 174 175 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 176 ARM_NS_DRAM1_BASE, \ 177 ARM_NS_DRAM1_SIZE, \ 178 MT_MEMORY | MT_RW | MT_NS) 179 180 #ifdef SPD_tspd 181 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 182 TSP_SEC_MEM_BASE, \ 183 TSP_SEC_MEM_SIZE, \ 184 MT_MEMORY | MT_RW | MT_SECURE) 185 #endif 186 187 #if ARM_BL31_IN_DRAM 188 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 189 BL31_BASE, \ 190 PLAT_ARM_MAX_BL31_SIZE, \ 191 MT_MEMORY | MT_RW | MT_SECURE) 192 #endif 193 194 /* 195 * The number of regions like RO(code), coherent and data required by 196 * different BL stages which need to be mapped in the MMU. 197 */ 198 #if USE_COHERENT_MEM 199 #define ARM_BL_REGIONS 3 200 #else 201 #define ARM_BL_REGIONS 2 202 #endif 203 204 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 205 ARM_BL_REGIONS) 206 207 /* Memory mapped Generic timer interfaces */ 208 #define ARM_SYS_CNTCTL_BASE 0x2a430000 209 #define ARM_SYS_CNTREAD_BASE 0x2a800000 210 #define ARM_SYS_TIMCTL_BASE 0x2a810000 211 212 #define ARM_CONSOLE_BAUDRATE 115200 213 214 /* Trusted Watchdog constants */ 215 #define ARM_SP805_TWDG_BASE 0x2a490000 216 #define ARM_SP805_TWDG_CLK_HZ 32768 217 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 218 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 219 #define ARM_TWDG_TIMEOUT_SEC 128 220 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 221 ARM_TWDG_TIMEOUT_SEC) 222 223 /****************************************************************************** 224 * Required platform porting definitions common to all ARM standard platforms 225 *****************************************************************************/ 226 227 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 228 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 229 230 /* 231 * This macro defines the deepest retention state possible. A higher state 232 * id will represent an invalid or a power down state. 233 */ 234 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 235 236 /* 237 * This macro defines the deepest power down states possible. Any state ID 238 * higher than this is invalid. 239 */ 240 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 241 242 /* 243 * Some data must be aligned on the biggest cache line size in the platform. 244 * This is known only to the platform as it might have a combination of 245 * integrated and external caches. 246 */ 247 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 248 249 250 /******************************************************************************* 251 * BL1 specific defines. 252 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 253 * addresses. 254 ******************************************************************************/ 255 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 256 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 257 + PLAT_ARM_TRUSTED_ROM_SIZE) 258 /* 259 * Put BL1 RW at the top of the Trusted SRAM. 260 */ 261 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 262 ARM_BL_RAM_SIZE - \ 263 PLAT_ARM_MAX_BL1_RW_SIZE) 264 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 265 266 /******************************************************************************* 267 * BL2 specific defines. 268 ******************************************************************************/ 269 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 270 /* 271 * For AArch32 BL31 is not applicable. 272 * For AArch64 BL31 is loaded in the DRAM. 273 * Put BL2 just below BL1. 274 */ 275 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 276 #define BL2_LIMIT BL1_RW_BASE 277 #else 278 /* 279 * Put BL2 just below BL31. 280 */ 281 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 282 #define BL2_LIMIT BL31_BASE 283 #endif 284 285 /******************************************************************************* 286 * BL31 specific defines. 287 ******************************************************************************/ 288 #if ARM_BL31_IN_DRAM 289 /* 290 * Put BL31 at the bottom of TZC secured DRAM 291 */ 292 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 293 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 294 PLAT_ARM_MAX_BL31_SIZE) 295 #elif (RESET_TO_BL31) 296 /* 297 * Put BL31_BASE in the middle of the Trusted SRAM. 298 */ 299 #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ 300 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) 301 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 302 #else 303 /* 304 * Put BL31 at the top of the Trusted SRAM. 305 */ 306 #define BL31_BASE (ARM_BL_RAM_BASE + \ 307 ARM_BL_RAM_SIZE - \ 308 PLAT_ARM_MAX_BL31_SIZE) 309 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 310 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 311 #endif 312 313 /******************************************************************************* 314 * BL32 specific defines. 315 ******************************************************************************/ 316 /* 317 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 318 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 319 * controller. 320 */ 321 #if ARM_BL31_IN_DRAM 322 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 323 PLAT_ARM_MAX_BL31_SIZE) 324 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 325 PLAT_ARM_MAX_BL31_SIZE) 326 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 327 PLAT_ARM_MAX_BL31_SIZE) 328 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 329 ARM_AP_TZC_DRAM1_SIZE) 330 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 331 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 332 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 333 # define TSP_PROGBITS_LIMIT BL2_BASE 334 # define BL32_BASE ARM_BL_RAM_BASE 335 # define BL32_LIMIT BL31_BASE 336 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 337 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 338 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 339 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 340 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 341 + (1 << 21)) 342 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 343 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 344 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 345 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 346 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 347 ARM_AP_TZC_DRAM1_SIZE) 348 #else 349 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 350 #endif 351 352 /* BL32 is mandatory in AArch32 */ 353 #ifndef AARCH32 354 #ifdef SPD_none 355 #undef BL32_BASE 356 #endif /* SPD_none */ 357 #endif 358 359 /******************************************************************************* 360 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 361 ******************************************************************************/ 362 #define BL2U_BASE BL2_BASE 363 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 364 /* 365 * For AArch32 BL31 is not applicable. 366 * For AArch64 BL31 is loaded in the DRAM. 367 * BL2U extends up to BL1. 368 */ 369 #define BL2U_LIMIT BL1_RW_BASE 370 #else 371 /* BL2U extends up to BL31. */ 372 #define BL2U_LIMIT BL31_BASE 373 #endif 374 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 375 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 376 377 /* 378 * ID of the secure physical generic timer interrupt used by the TSP. 379 */ 380 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 381 382 383 /* 384 * One cache line needed for bakery locks on ARM platforms 385 */ 386 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 387 388 389 #endif /* __ARM_DEF_H__ */ 390