1 /* 2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/common/smccc_def.h> 16 #include <plat/common/common_def.h> 17 18 /****************************************************************************** 19 * Definitions common to all ARM standard platforms 20 *****************************************************************************/ 21 22 /* 23 * Root of trust key lengths 24 */ 25 #define ARM_ROTPK_HEADER_LEN 19 26 #define ARM_ROTPK_HASH_LEN 32 27 /* ARM_ROTPK_KEY_LEN includes DER header + raw key material */ 28 #define ARM_ROTPK_KEY_LEN 294 29 30 /* Special value used to verify platform parameters from BL2 to BL31 */ 31 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 32 33 #define ARM_SYSTEM_COUNT U(1) 34 35 #define ARM_CACHE_WRITEBACK_SHIFT 6 36 37 /* 38 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 39 * power levels have a 1:1 mapping with the MPIDR affinity levels. 40 */ 41 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 42 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 43 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 44 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 45 46 /* 47 * Macros for local power states in ARM platforms encoded by State-ID field 48 * within the power-state parameter. 49 */ 50 /* Local power state for power domains in Run state. */ 51 #define ARM_LOCAL_STATE_RUN U(0) 52 /* Local power state for retention. Valid only for CPU power domains */ 53 #define ARM_LOCAL_STATE_RET U(1) 54 /* Local power state for OFF/power-down. Valid for CPU and cluster power 55 domains */ 56 #define ARM_LOCAL_STATE_OFF U(2) 57 58 /* Memory location options for TSP */ 59 #define ARM_TRUSTED_SRAM_ID 0 60 #define ARM_TRUSTED_DRAM_ID 1 61 #define ARM_DRAM_ID 2 62 63 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 64 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 65 #else 66 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 67 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 68 69 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 70 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 71 72 /* The remaining Trusted SRAM is used to load the BL images */ 73 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 74 ARM_SHARED_RAM_SIZE) 75 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 76 ARM_SHARED_RAM_SIZE) 77 78 /* 79 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 80 * follows: 81 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 82 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 83 * - REALM DRAM: Reserved for Realm world if RME is enabled 84 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 85 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 86 * 87 * RME enabled(64MB) RME not enabled(16MB) 88 * -------------------- ------------------- 89 * | | | | 90 * | AP TZC (~28MB) | | AP TZC (~14MB) | 91 * -------------------- ------------------- 92 * | | | | 93 * | REALM (RMM) | | EL3 TZC (2MB) | 94 * | (32MB - 4KB) | ------------------- 95 * -------------------- | | 96 * | | | SCP TZC | 97 * | TF-A <-> RMM | 0xFFFF_FFFF------------------- 98 * | SHARED (4KB) | 99 * -------------------- 100 * | | 101 * | EL3 TZC (3MB) | 102 * -------------------- 103 * | L1 GPT + SCP TZC | 104 * | (~1MB) | 105 * 0xFFFF_FFFF -------------------- 106 */ 107 #if ENABLE_RME 108 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 109 /* 110 * Define a region within the TZC secured DRAM for use by EL3 runtime 111 * firmware. This region is meant to be NOLOAD and will not be zero 112 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 113 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 114 */ 115 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 116 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 117 118 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 119 #define ARM_REALM_SIZE (UL(0x02000000) - \ 120 ARM_EL3_RMM_SHARED_SIZE) 121 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 122 #else 123 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 124 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 125 #define ARM_L1_GPT_SIZE UL(0) 126 #define ARM_REALM_SIZE UL(0) 127 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 128 #endif /* ENABLE_RME */ 129 130 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 131 ARM_DRAM1_SIZE - \ 132 (ARM_SCP_TZC_DRAM1_SIZE + \ 133 ARM_L1_GPT_SIZE)) 134 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 135 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 136 ARM_SCP_TZC_DRAM1_SIZE - 1U) 137 #if ENABLE_RME 138 #define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \ 139 ARM_DRAM1_SIZE - \ 140 ARM_L1_GPT_SIZE) 141 #define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \ 142 ARM_L1_GPT_SIZE - 1U) 143 144 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 145 ARM_REALM_SIZE) 146 147 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 148 149 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 150 ARM_DRAM1_SIZE - \ 151 (ARM_SCP_TZC_DRAM1_SIZE + \ 152 ARM_L1_GPT_SIZE + \ 153 ARM_EL3_RMM_SHARED_SIZE + \ 154 ARM_EL3_TZC_DRAM1_SIZE)) 155 156 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 157 ARM_EL3_RMM_SHARED_SIZE - 1U) 158 #endif /* ENABLE_RME */ 159 160 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 161 ARM_EL3_TZC_DRAM1_SIZE) 162 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 163 ARM_EL3_TZC_DRAM1_SIZE - 1U) 164 165 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 166 ARM_DRAM1_SIZE - \ 167 ARM_TZC_DRAM1_SIZE) 168 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 169 (ARM_SCP_TZC_DRAM1_SIZE + \ 170 ARM_EL3_TZC_DRAM1_SIZE + \ 171 ARM_EL3_RMM_SHARED_SIZE + \ 172 ARM_REALM_SIZE + \ 173 ARM_L1_GPT_SIZE)) 174 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 175 ARM_AP_TZC_DRAM1_SIZE - 1U) 176 177 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 178 #if ARM_CRYPTOCELL_INTEG 179 /* 180 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 181 * This is required by CryptoCell to authenticate BL33 which is loaded 182 * into the Non Secure DDR. 183 */ 184 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 185 #else 186 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 187 #endif 188 189 #ifdef SPD_opteed 190 /* 191 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 192 * load/authenticate the trusted os extra image. The first 512KB of 193 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 194 * for OPTEE is paged image which only include the paging part using 195 * virtual memory but without "init" data. OPTEE will copy the "init" data 196 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 197 * extra image behind the "init" data. 198 */ 199 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 200 ARM_AP_TZC_DRAM1_SIZE - \ 201 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 202 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 203 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 204 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 205 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 206 MT_MEMORY | MT_RW | MT_SECURE) 207 208 /* 209 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 210 * support is enabled). 211 */ 212 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 213 BL32_BASE, \ 214 BL32_LIMIT - BL32_BASE, \ 215 MT_MEMORY | MT_RW | MT_SECURE) 216 #endif /* SPD_opteed */ 217 218 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 219 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 220 ARM_TZC_DRAM1_SIZE) 221 222 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 223 ARM_NS_DRAM1_SIZE - 1U) 224 #ifdef PLAT_ARM_DRAM1_BASE 225 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 226 #else 227 #define ARM_DRAM1_BASE ULL(0x80000000) 228 #endif /* PLAT_ARM_DRAM1_BASE */ 229 230 #define ARM_DRAM1_SIZE ULL(0x80000000) 231 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 232 ARM_DRAM1_SIZE - 1U) 233 234 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 235 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 236 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 237 ARM_DRAM2_SIZE - 1U) 238 /* Number of DRAM banks */ 239 #define ARM_DRAM_NUM_BANKS 2UL 240 241 #define ARM_IRQ_SEC_PHY_TIMER 29 242 243 #define ARM_IRQ_SEC_SGI_0 8 244 #define ARM_IRQ_SEC_SGI_1 9 245 #define ARM_IRQ_SEC_SGI_2 10 246 #define ARM_IRQ_SEC_SGI_3 11 247 #define ARM_IRQ_SEC_SGI_4 12 248 #define ARM_IRQ_SEC_SGI_5 13 249 #define ARM_IRQ_SEC_SGI_6 14 250 #define ARM_IRQ_SEC_SGI_7 15 251 252 /* 253 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 254 * terminology. On a GICv2 system or mode, the lists will be merged and treated 255 * as Group 0 interrupts. 256 */ 257 #define ARM_G1S_IRQ_PROPS(grp) \ 258 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 259 GIC_INTR_CFG_LEVEL), \ 260 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 261 GIC_INTR_CFG_EDGE), \ 262 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 263 GIC_INTR_CFG_EDGE), \ 264 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 265 GIC_INTR_CFG_EDGE), \ 266 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 267 GIC_INTR_CFG_EDGE), \ 268 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 269 GIC_INTR_CFG_EDGE), \ 270 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 271 GIC_INTR_CFG_EDGE) 272 273 #define ARM_G0_IRQ_PROPS(grp) \ 274 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 275 GIC_INTR_CFG_EDGE), \ 276 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 277 GIC_INTR_CFG_EDGE) 278 279 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 280 ARM_SHARED_RAM_BASE, \ 281 ARM_SHARED_RAM_SIZE, \ 282 MT_DEVICE | MT_RW | EL3_PAS) 283 284 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 285 ARM_NS_DRAM1_BASE, \ 286 ARM_NS_DRAM1_SIZE, \ 287 MT_MEMORY | MT_RW | MT_NS) 288 289 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 290 ARM_DRAM2_BASE, \ 291 ARM_DRAM2_SIZE, \ 292 MT_MEMORY | MT_RW | MT_NS) 293 294 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 295 TSP_SEC_MEM_BASE, \ 296 TSP_SEC_MEM_SIZE, \ 297 MT_MEMORY | MT_RW | MT_SECURE) 298 299 #if ARM_BL31_IN_DRAM 300 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 301 BL31_BASE, \ 302 PLAT_ARM_MAX_BL31_SIZE, \ 303 MT_MEMORY | MT_RW | MT_SECURE) 304 #endif 305 306 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 307 ARM_EL3_TZC_DRAM1_BASE, \ 308 ARM_EL3_TZC_DRAM1_SIZE, \ 309 MT_MEMORY | MT_RW | EL3_PAS) 310 311 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 312 PLAT_ARM_TRUSTED_DRAM_BASE, \ 313 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 314 MT_MEMORY | MT_RW | MT_SECURE) 315 316 #if ENABLE_RME 317 /* 318 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 319 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 320 */ 321 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 322 PLAT_ARM_RMM_BASE, \ 323 (PLAT_ARM_RMM_SIZE + \ 324 ARM_EL3_RMM_SHARED_SIZE), \ 325 MT_MEMORY | MT_RW | MT_REALM) 326 327 328 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 329 ARM_L1_GPT_ADDR_BASE, \ 330 ARM_L1_GPT_SIZE, \ 331 MT_MEMORY | MT_RW | EL3_PAS) 332 333 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 334 MAP_REGION_FLAT( \ 335 ARM_EL3_RMM_SHARED_BASE, \ 336 ARM_EL3_RMM_SHARED_SIZE, \ 337 MT_MEMORY | MT_RW | MT_REALM) 338 339 #endif /* ENABLE_RME */ 340 341 /* 342 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 343 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 344 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 345 * to be able to access the heap. 346 */ 347 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 348 BL1_RW_BASE, \ 349 BL1_RW_LIMIT - BL1_RW_BASE, \ 350 MT_MEMORY | MT_RW | EL3_PAS) 351 352 /* 353 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 354 * otherwise one region is defined containing both. 355 */ 356 #if SEPARATE_CODE_AND_RODATA 357 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 358 BL_CODE_BASE, \ 359 BL_CODE_END - BL_CODE_BASE, \ 360 MT_CODE | EL3_PAS), \ 361 MAP_REGION_FLAT( \ 362 BL_RO_DATA_BASE, \ 363 BL_RO_DATA_END \ 364 - BL_RO_DATA_BASE, \ 365 MT_RO_DATA | EL3_PAS) 366 #else 367 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 368 BL_CODE_BASE, \ 369 BL_CODE_END - BL_CODE_BASE, \ 370 MT_CODE | EL3_PAS) 371 #endif 372 #if USE_COHERENT_MEM 373 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 374 BL_COHERENT_RAM_BASE, \ 375 BL_COHERENT_RAM_END \ 376 - BL_COHERENT_RAM_BASE, \ 377 MT_DEVICE | MT_RW | EL3_PAS) 378 #endif 379 #if USE_ROMLIB 380 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 381 ROMLIB_RO_BASE, \ 382 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 383 MT_CODE | EL3_PAS) 384 385 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 386 ROMLIB_RW_BASE, \ 387 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 388 MT_MEMORY | MT_RW | EL3_PAS) 389 #endif 390 391 /* 392 * Map mem_protect flash region with read and write permissions 393 */ 394 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 395 V2M_FLASH_BLOCK_SIZE, \ 396 MT_DEVICE | MT_RW | MT_SECURE) 397 /* 398 * Map the region for device tree configuration with read and write permissions 399 */ 400 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 401 (ARM_FW_CONFIGS_LIMIT \ 402 - ARM_BL_RAM_BASE), \ 403 MT_MEMORY | MT_RW | EL3_PAS) 404 /* 405 * Map L0_GPT with read and write permissions 406 */ 407 #if ENABLE_RME 408 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \ 409 ARM_L0_GPT_SIZE, \ 410 MT_MEMORY | MT_RW | MT_ROOT) 411 #endif 412 413 /* 414 * The max number of regions like RO(code), coherent and data required by 415 * different BL stages which need to be mapped in the MMU. 416 */ 417 #define ARM_BL_REGIONS 7 418 419 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 420 ARM_BL_REGIONS) 421 422 /* Memory mapped Generic timer interfaces */ 423 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 424 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 425 #else 426 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 427 #endif 428 429 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 430 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 431 #else 432 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 433 #endif 434 435 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 436 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 437 #else 438 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 439 #endif 440 441 #ifdef PLAT_ARM_SYS_CNT_BASE_S 442 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 443 #else 444 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 445 #endif 446 447 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 448 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 449 #else 450 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 451 #endif 452 453 #define ARM_CONSOLE_BAUDRATE 115200 454 455 /* Trusted Watchdog constants */ 456 #ifdef PLAT_ARM_SP805_TWDG_BASE 457 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 458 #else 459 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 460 #endif 461 #define ARM_SP805_TWDG_CLK_HZ 32768 462 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 463 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 464 #define ARM_TWDG_TIMEOUT_SEC 128 465 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 466 ARM_TWDG_TIMEOUT_SEC) 467 468 /****************************************************************************** 469 * Required platform porting definitions common to all ARM standard platforms 470 *****************************************************************************/ 471 472 /* 473 * This macro defines the deepest retention state possible. A higher state 474 * id will represent an invalid or a power down state. 475 */ 476 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 477 478 /* 479 * This macro defines the deepest power down states possible. Any state ID 480 * higher than this is invalid. 481 */ 482 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 483 484 /* 485 * Some data must be aligned on the biggest cache line size in the platform. 486 * This is known only to the platform as it might have a combination of 487 * integrated and external caches. 488 */ 489 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 490 491 /* 492 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 493 * and limit. Leave enough space of BL2 meminfo. 494 */ 495 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 496 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 497 + (PAGE_SIZE / 2U)) 498 499 /* 500 * Boot parameters passed from BL2 to BL31/BL32 are stored here 501 */ 502 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 503 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 504 + (PAGE_SIZE / 2U)) 505 506 /* 507 * Define limit of firmware configuration memory: 508 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 509 */ 510 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) 511 512 #if ENABLE_RME 513 /* 514 * Store the L0 GPT on Trusted SRAM next to firmware 515 * configuration memory, 4KB aligned. 516 */ 517 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 518 #define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT) 519 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE) 520 #else 521 #define ARM_L0_GPT_SIZE U(0) 522 #endif 523 524 /******************************************************************************* 525 * BL1 specific defines. 526 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 527 * addresses. 528 ******************************************************************************/ 529 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 530 #ifdef PLAT_BL1_RO_LIMIT 531 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 532 #else 533 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 534 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 535 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 536 #endif 537 538 /* 539 * Put BL1 RW at the top of the Trusted SRAM. 540 */ 541 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 542 ARM_BL_RAM_SIZE - \ 543 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 544 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 545 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 546 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 547 548 #define ROMLIB_RO_BASE BL1_RO_LIMIT 549 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 550 551 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 552 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 553 554 /******************************************************************************* 555 * BL2 specific defines. 556 ******************************************************************************/ 557 #if BL2_AT_EL3 558 #if ENABLE_PIE 559 /* 560 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 561 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 562 */ 563 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 564 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 565 0x3000) 566 #else 567 /* Put BL2 towards the middle of the Trusted SRAM */ 568 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 569 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 570 0x2000) 571 #endif /* ENABLE_PIE */ 572 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 573 574 #else 575 /* 576 * Put BL2 just below BL1. 577 */ 578 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 579 #define BL2_LIMIT BL1_RW_BASE 580 #endif 581 582 /******************************************************************************* 583 * BL31 specific defines. 584 ******************************************************************************/ 585 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 586 /* 587 * Put BL31 at the bottom of TZC secured DRAM 588 */ 589 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 590 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 591 PLAT_ARM_MAX_BL31_SIZE) 592 /* 593 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 594 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 595 */ 596 #if SEPARATE_NOBITS_REGION 597 #define BL31_NOBITS_BASE BL2_BASE 598 #define BL31_NOBITS_LIMIT BL2_LIMIT 599 #endif /* SEPARATE_NOBITS_REGION */ 600 #elif (RESET_TO_BL31) 601 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 602 # if !ENABLE_PIE 603 # error "BL31 must be a PIE if RESET_TO_BL31=1." 604 #endif 605 /* 606 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 607 * used for building BL31 and not used for loading BL31. 608 */ 609 # define BL31_BASE 0x0 610 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 611 #else 612 /* Put BL31 below BL2 in the Trusted SRAM.*/ 613 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 614 - PLAT_ARM_MAX_BL31_SIZE) 615 #define BL31_PROGBITS_LIMIT BL2_BASE 616 /* 617 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 618 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 619 */ 620 #if BL2_AT_EL3 621 #define BL31_LIMIT BL2_BASE 622 #else 623 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 624 #endif 625 #endif 626 627 /****************************************************************************** 628 * RMM specific defines 629 *****************************************************************************/ 630 #if ENABLE_RME 631 #define RMM_BASE (ARM_REALM_BASE) 632 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 633 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 634 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 635 #endif 636 637 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 638 /******************************************************************************* 639 * BL32 specific defines for EL3 runtime in AArch32 mode 640 ******************************************************************************/ 641 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 642 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 643 # if !ENABLE_PIE 644 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 645 #endif 646 /* 647 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 648 * used for building BL32 and not used for loading BL32. 649 */ 650 # define BL32_BASE 0x0 651 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 652 # else 653 /* Put BL32 below BL2 in the Trusted SRAM.*/ 654 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 655 - PLAT_ARM_MAX_BL32_SIZE) 656 # define BL32_PROGBITS_LIMIT BL2_BASE 657 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 658 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 659 660 #else 661 /******************************************************************************* 662 * BL32 specific defines for EL3 runtime in AArch64 mode 663 ******************************************************************************/ 664 /* 665 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 666 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 667 * controller. 668 */ 669 # if SPM_MM || SPMC_AT_EL3 670 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 671 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 672 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 673 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 674 ARM_AP_TZC_DRAM1_SIZE) 675 # elif defined(SPD_spmd) 676 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 677 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 678 # define BL32_BASE PLAT_ARM_SPMC_BASE 679 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 680 PLAT_ARM_SPMC_SIZE) 681 # elif ARM_BL31_IN_DRAM 682 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 683 PLAT_ARM_MAX_BL31_SIZE) 684 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 685 PLAT_ARM_MAX_BL31_SIZE) 686 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 687 PLAT_ARM_MAX_BL31_SIZE) 688 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 689 ARM_AP_TZC_DRAM1_SIZE) 690 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 691 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 692 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 693 # define TSP_PROGBITS_LIMIT BL31_BASE 694 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 695 # define BL32_LIMIT BL31_BASE 696 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 697 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 698 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 699 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 700 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 701 + (UL(1) << 21)) 702 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 703 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 704 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 705 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 706 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 707 ARM_AP_TZC_DRAM1_SIZE) 708 # else 709 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 710 # endif 711 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 712 713 /* 714 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 715 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 716 * used as BL32. 717 */ 718 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 719 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 720 # undef BL32_BASE 721 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 722 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 723 724 /******************************************************************************* 725 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 726 ******************************************************************************/ 727 #define BL2U_BASE BL2_BASE 728 #define BL2U_LIMIT BL2_LIMIT 729 730 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 731 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 732 733 /* 734 * ID of the secure physical generic timer interrupt used by the TSP. 735 */ 736 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 737 738 739 /* 740 * One cache line needed for bakery locks on ARM platforms 741 */ 742 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 743 744 /* Priority levels for ARM platforms */ 745 #define PLAT_RAS_PRI 0x10 746 #define PLAT_SDEI_CRITICAL_PRI 0x60 747 #define PLAT_SDEI_NORMAL_PRI 0x70 748 749 /* ARM platforms use 3 upper bits of secure interrupt priority */ 750 #define PLAT_PRI_BITS 3 751 752 /* SGI used for SDEI signalling */ 753 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 754 755 #if SDEI_IN_FCONF 756 /* ARM SDEI dynamic private event max count */ 757 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 758 759 /* ARM SDEI dynamic shared event max count */ 760 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 761 #else 762 /* ARM SDEI dynamic private event numbers */ 763 #define ARM_SDEI_DP_EVENT_0 1000 764 #define ARM_SDEI_DP_EVENT_1 1001 765 #define ARM_SDEI_DP_EVENT_2 1002 766 767 /* ARM SDEI dynamic shared event numbers */ 768 #define ARM_SDEI_DS_EVENT_0 2000 769 #define ARM_SDEI_DS_EVENT_1 2001 770 #define ARM_SDEI_DS_EVENT_2 2002 771 772 #define ARM_SDEI_PRIVATE_EVENTS \ 773 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 774 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 775 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 776 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 777 778 #define ARM_SDEI_SHARED_EVENTS \ 779 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 780 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 781 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 782 #endif /* SDEI_IN_FCONF */ 783 784 #endif /* ARM_DEF_H */ 785