1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <platform_def.h> 14 #include <tbbr_img_def.h> 15 #include <utils_def.h> 16 #include <xlat_tables_defs.h> 17 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 25 26 #define ARM_SYSTEM_COUNT 1 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 38 /* 39 * Macros for local power states in ARM platforms encoded by State-ID field 40 * within the power-state parameter. 41 */ 42 /* Local power state for power domains in Run state. */ 43 #define ARM_LOCAL_STATE_RUN 0 44 /* Local power state for retention. Valid only for CPU power domains */ 45 #define ARM_LOCAL_STATE_RET 1 46 /* Local power state for OFF/power-down. Valid for CPU and cluster power 47 domains */ 48 #define ARM_LOCAL_STATE_OFF 2 49 50 /* Memory location options for TSP */ 51 #define ARM_TRUSTED_SRAM_ID 0 52 #define ARM_TRUSTED_DRAM_ID 1 53 #define ARM_DRAM_ID 2 54 55 /* The first 4KB of Trusted SRAM are used as shared memory */ 56 #define ARM_TRUSTED_SRAM_BASE 0x04000000 57 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 58 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 59 60 /* The remaining Trusted SRAM is used to load the BL images */ 61 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 62 ARM_SHARED_RAM_SIZE) 63 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 64 ARM_SHARED_RAM_SIZE) 65 66 /* 67 * The top 16MB of DRAM1 is configured as secure access only using the TZC 68 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 69 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 70 */ 71 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 72 73 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 74 ARM_DRAM1_SIZE - \ 75 ARM_SCP_TZC_DRAM1_SIZE) 76 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 77 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 78 ARM_SCP_TZC_DRAM1_SIZE - 1) 79 80 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 81 ARM_DRAM1_SIZE - \ 82 ARM_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 84 ARM_SCP_TZC_DRAM1_SIZE) 85 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 86 ARM_AP_TZC_DRAM1_SIZE - 1) 87 88 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 89 #if ARM_CRYPTOCELL_INTEG 90 /* 91 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 92 * This is required by CryptoCell to authenticate BL33 which is loaded 93 * into the Non Secure DDR. 94 */ 95 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 96 #else 97 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 98 #endif 99 100 #ifdef SPD_opteed 101 /* 102 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 103 * load/authenticate the trusted os extra image. The first 512KB of 104 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 105 * for OPTEE is paged image which only include the paging part using 106 * virtual memory but without "init" data. OPTEE will copy the "init" data 107 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 108 * extra image behind the "init" data. 109 */ 110 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 111 ARM_AP_TZC_DRAM1_SIZE - \ 112 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 113 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 114 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 115 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 116 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 117 MT_MEMORY | MT_RW | MT_SECURE) 118 119 /* 120 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 121 * support is enabled). 122 */ 123 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 124 BL32_BASE, \ 125 BL32_LIMIT - BL32_BASE, \ 126 MT_MEMORY | MT_RW | MT_SECURE) 127 #endif /* SPD_opteed */ 128 129 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 130 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 131 ARM_TZC_DRAM1_SIZE) 132 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 133 ARM_NS_DRAM1_SIZE - 1) 134 135 #define ARM_DRAM1_BASE ULL(0x80000000) 136 #define ARM_DRAM1_SIZE ULL(0x80000000) 137 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 138 ARM_DRAM1_SIZE - 1) 139 140 #define ARM_DRAM2_BASE ULL(0x880000000) 141 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 142 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 143 ARM_DRAM2_SIZE - 1) 144 145 #define ARM_IRQ_SEC_PHY_TIMER 29 146 147 #define ARM_IRQ_SEC_SGI_0 8 148 #define ARM_IRQ_SEC_SGI_1 9 149 #define ARM_IRQ_SEC_SGI_2 10 150 #define ARM_IRQ_SEC_SGI_3 11 151 #define ARM_IRQ_SEC_SGI_4 12 152 #define ARM_IRQ_SEC_SGI_5 13 153 #define ARM_IRQ_SEC_SGI_6 14 154 #define ARM_IRQ_SEC_SGI_7 15 155 156 /* 157 * List of secure interrupts are deprecated, but are retained only to support 158 * legacy configurations. 159 */ 160 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 161 ARM_IRQ_SEC_SGI_1, \ 162 ARM_IRQ_SEC_SGI_2, \ 163 ARM_IRQ_SEC_SGI_3, \ 164 ARM_IRQ_SEC_SGI_4, \ 165 ARM_IRQ_SEC_SGI_5, \ 166 ARM_IRQ_SEC_SGI_7 167 168 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 169 ARM_IRQ_SEC_SGI_6 170 171 /* 172 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 173 * terminology. On a GICv2 system or mode, the lists will be merged and treated 174 * as Group 0 interrupts. 175 */ 176 #define ARM_G1S_IRQ_PROPS(grp) \ 177 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 178 GIC_INTR_CFG_LEVEL), \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 180 GIC_INTR_CFG_EDGE), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 182 GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 184 GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 186 GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 188 GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 190 GIC_INTR_CFG_EDGE) 191 192 #define ARM_G0_IRQ_PROPS(grp) \ 193 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 194 GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 196 GIC_INTR_CFG_EDGE) 197 198 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 199 ARM_SHARED_RAM_BASE, \ 200 ARM_SHARED_RAM_SIZE, \ 201 MT_DEVICE | MT_RW | MT_SECURE) 202 203 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 204 ARM_NS_DRAM1_BASE, \ 205 ARM_NS_DRAM1_SIZE, \ 206 MT_MEMORY | MT_RW | MT_NS) 207 208 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 209 ARM_DRAM2_BASE, \ 210 ARM_DRAM2_SIZE, \ 211 MT_MEMORY | MT_RW | MT_NS) 212 #ifdef SPD_tspd 213 214 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 215 TSP_SEC_MEM_BASE, \ 216 TSP_SEC_MEM_SIZE, \ 217 MT_MEMORY | MT_RW | MT_SECURE) 218 #endif 219 220 #if ARM_BL31_IN_DRAM 221 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 222 BL31_BASE, \ 223 PLAT_ARM_MAX_BL31_SIZE, \ 224 MT_MEMORY | MT_RW | MT_SECURE) 225 #endif 226 227 /* 228 * The number of regions like RO(code), coherent and data required by 229 * different BL stages which need to be mapped in the MMU. 230 */ 231 #if USE_COHERENT_MEM 232 #define ARM_BL_REGIONS 3 233 #else 234 #define ARM_BL_REGIONS 2 235 #endif 236 237 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 238 ARM_BL_REGIONS) 239 240 /* Memory mapped Generic timer interfaces */ 241 #define ARM_SYS_CNTCTL_BASE 0x2a430000 242 #define ARM_SYS_CNTREAD_BASE 0x2a800000 243 #define ARM_SYS_TIMCTL_BASE 0x2a810000 244 245 #define ARM_CONSOLE_BAUDRATE 115200 246 247 /* Trusted Watchdog constants */ 248 #define ARM_SP805_TWDG_BASE 0x2a490000 249 #define ARM_SP805_TWDG_CLK_HZ 32768 250 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 251 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 252 #define ARM_TWDG_TIMEOUT_SEC 128 253 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 254 ARM_TWDG_TIMEOUT_SEC) 255 256 /****************************************************************************** 257 * Required platform porting definitions common to all ARM standard platforms 258 *****************************************************************************/ 259 260 /* 261 * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for 262 * AArch64 builds 263 */ 264 #ifdef AARCH64 265 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 36) 266 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 36) 267 #else 268 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 269 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 270 #endif 271 272 273 /* 274 * This macro defines the deepest retention state possible. A higher state 275 * id will represent an invalid or a power down state. 276 */ 277 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 278 279 /* 280 * This macro defines the deepest power down states possible. Any state ID 281 * higher than this is invalid. 282 */ 283 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 284 285 /* 286 * Some data must be aligned on the biggest cache line size in the platform. 287 * This is known only to the platform as it might have a combination of 288 * integrated and external caches. 289 */ 290 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 291 292 293 /******************************************************************************* 294 * BL1 specific defines. 295 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 296 * addresses. 297 ******************************************************************************/ 298 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 299 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 300 + PLAT_ARM_TRUSTED_ROM_SIZE) 301 /* 302 * Put BL1 RW at the top of the Trusted SRAM. 303 */ 304 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 305 ARM_BL_RAM_SIZE - \ 306 PLAT_ARM_MAX_BL1_RW_SIZE) 307 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 308 309 /******************************************************************************* 310 * BL2 specific defines. 311 ******************************************************************************/ 312 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 313 /* 314 * For AArch32 BL31 is not applicable. 315 * For AArch64 BL31 is loaded in the DRAM. 316 * Put BL2 just below BL1. 317 */ 318 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 319 #define BL2_LIMIT BL1_RW_BASE 320 #else 321 /* 322 * Put BL2 just below BL31. 323 */ 324 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 325 #define BL2_LIMIT BL31_BASE 326 #endif 327 328 /******************************************************************************* 329 * BL31 specific defines. 330 ******************************************************************************/ 331 #if ARM_BL31_IN_DRAM 332 /* 333 * Put BL31 at the bottom of TZC secured DRAM 334 */ 335 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 336 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 337 PLAT_ARM_MAX_BL31_SIZE) 338 #elif (RESET_TO_BL31) 339 /* 340 * Put BL31_BASE in the middle of the Trusted SRAM. 341 */ 342 #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ 343 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) 344 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 345 #else 346 /* 347 * Put BL31 at the top of the Trusted SRAM. 348 */ 349 #define BL31_BASE (ARM_BL_RAM_BASE + \ 350 ARM_BL_RAM_SIZE - \ 351 PLAT_ARM_MAX_BL31_SIZE) 352 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 353 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 354 #endif 355 356 /******************************************************************************* 357 * BL32 specific defines. 358 ******************************************************************************/ 359 /* 360 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 361 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 362 * controller. 363 */ 364 #if ARM_BL31_IN_DRAM 365 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 366 PLAT_ARM_MAX_BL31_SIZE) 367 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 368 PLAT_ARM_MAX_BL31_SIZE) 369 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 370 PLAT_ARM_MAX_BL31_SIZE) 371 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 372 ARM_AP_TZC_DRAM1_SIZE) 373 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 374 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 375 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 376 # define TSP_PROGBITS_LIMIT BL2_BASE 377 # define BL32_BASE ARM_BL_RAM_BASE 378 # define BL32_LIMIT BL31_BASE 379 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 380 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 381 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 382 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 383 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 384 + (1 << 21)) 385 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 386 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 387 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 388 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 389 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 390 ARM_AP_TZC_DRAM1_SIZE) 391 #else 392 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 393 #endif 394 395 /* BL32 is mandatory in AArch32 */ 396 #ifndef AARCH32 397 #ifdef SPD_none 398 #undef BL32_BASE 399 #endif /* SPD_none */ 400 #endif 401 402 /******************************************************************************* 403 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 404 ******************************************************************************/ 405 #define BL2U_BASE BL2_BASE 406 #if ARM_BL31_IN_DRAM || (defined(AARCH32) && !defined(JUNO_AARCH32_EL3_RUNTIME)) 407 /* 408 * For AArch32 BL31 is not applicable. 409 * For AArch64 BL31 is loaded in the DRAM. 410 * BL2U extends up to BL1. 411 */ 412 #define BL2U_LIMIT BL1_RW_BASE 413 #else 414 /* BL2U extends up to BL31. */ 415 #define BL2U_LIMIT BL31_BASE 416 #endif 417 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 418 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 419 420 /* 421 * ID of the secure physical generic timer interrupt used by the TSP. 422 */ 423 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 424 425 426 /* 427 * One cache line needed for bakery locks on ARM platforms 428 */ 429 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 430 431 432 #endif /* __ARM_DEF_H__ */ 433