1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <platform_def.h> 14 #include <tbbr_img_def.h> 15 #include <utils_def.h> 16 #include <xlat_tables_defs.h> 17 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 25 26 #define ARM_SYSTEM_COUNT 1 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 38 /* 39 * Macros for local power states in ARM platforms encoded by State-ID field 40 * within the power-state parameter. 41 */ 42 /* Local power state for power domains in Run state. */ 43 #define ARM_LOCAL_STATE_RUN U(0) 44 /* Local power state for retention. Valid only for CPU power domains */ 45 #define ARM_LOCAL_STATE_RET U(1) 46 /* Local power state for OFF/power-down. Valid for CPU and cluster power 47 domains */ 48 #define ARM_LOCAL_STATE_OFF U(2) 49 50 /* Memory location options for TSP */ 51 #define ARM_TRUSTED_SRAM_ID 0 52 #define ARM_TRUSTED_DRAM_ID 1 53 #define ARM_DRAM_ID 2 54 55 /* The first 4KB of Trusted SRAM are used as shared memory */ 56 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 57 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 58 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 59 60 /* The remaining Trusted SRAM is used to load the BL images */ 61 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 62 ARM_SHARED_RAM_SIZE) 63 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 64 ARM_SHARED_RAM_SIZE) 65 66 /* 67 * The top 16MB of DRAM1 is configured as secure access only using the TZC 68 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 69 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 70 */ 71 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 72 73 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 74 ARM_DRAM1_SIZE - \ 75 ARM_SCP_TZC_DRAM1_SIZE) 76 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 77 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 78 ARM_SCP_TZC_DRAM1_SIZE - 1) 79 80 /* 81 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 82 * firmware. This region is meant to be NOLOAD and will not be zero 83 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 84 * placed here. 85 */ 86 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 87 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 88 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 89 ARM_EL3_TZC_DRAM1_SIZE - 1) 90 91 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 92 ARM_DRAM1_SIZE - \ 93 ARM_TZC_DRAM1_SIZE) 94 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 95 (ARM_SCP_TZC_DRAM1_SIZE + \ 96 ARM_EL3_TZC_DRAM1_SIZE)) 97 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 98 ARM_AP_TZC_DRAM1_SIZE - 1) 99 100 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 101 #if ARM_CRYPTOCELL_INTEG 102 /* 103 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 104 * This is required by CryptoCell to authenticate BL33 which is loaded 105 * into the Non Secure DDR. 106 */ 107 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 108 #else 109 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 110 #endif 111 112 #ifdef SPD_opteed 113 /* 114 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 115 * load/authenticate the trusted os extra image. The first 512KB of 116 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 117 * for OPTEE is paged image which only include the paging part using 118 * virtual memory but without "init" data. OPTEE will copy the "init" data 119 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 120 * extra image behind the "init" data. 121 */ 122 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 123 ARM_AP_TZC_DRAM1_SIZE - \ 124 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 125 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 126 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 127 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 128 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 129 MT_MEMORY | MT_RW | MT_SECURE) 130 131 /* 132 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 133 * support is enabled). 134 */ 135 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 136 BL32_BASE, \ 137 BL32_LIMIT - BL32_BASE, \ 138 MT_MEMORY | MT_RW | MT_SECURE) 139 #endif /* SPD_opteed */ 140 141 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 142 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 143 ARM_TZC_DRAM1_SIZE) 144 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 145 ARM_NS_DRAM1_SIZE - 1) 146 147 #define ARM_DRAM1_BASE UL(0x80000000) 148 #define ARM_DRAM1_SIZE UL(0x80000000) 149 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 150 ARM_DRAM1_SIZE - 1) 151 152 #define ARM_DRAM2_BASE UL(0x880000000) 153 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 154 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 155 ARM_DRAM2_SIZE - 1) 156 157 #define ARM_IRQ_SEC_PHY_TIMER 29 158 159 #define ARM_IRQ_SEC_SGI_0 8 160 #define ARM_IRQ_SEC_SGI_1 9 161 #define ARM_IRQ_SEC_SGI_2 10 162 #define ARM_IRQ_SEC_SGI_3 11 163 #define ARM_IRQ_SEC_SGI_4 12 164 #define ARM_IRQ_SEC_SGI_5 13 165 #define ARM_IRQ_SEC_SGI_6 14 166 #define ARM_IRQ_SEC_SGI_7 15 167 168 /* 169 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 170 * terminology. On a GICv2 system or mode, the lists will be merged and treated 171 * as Group 0 interrupts. 172 */ 173 #define ARM_G1S_IRQ_PROPS(grp) \ 174 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 175 GIC_INTR_CFG_LEVEL), \ 176 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 177 GIC_INTR_CFG_EDGE), \ 178 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 179 GIC_INTR_CFG_EDGE), \ 180 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 181 GIC_INTR_CFG_EDGE), \ 182 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 183 GIC_INTR_CFG_EDGE), \ 184 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 185 GIC_INTR_CFG_EDGE), \ 186 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 187 GIC_INTR_CFG_EDGE) 188 189 #define ARM_G0_IRQ_PROPS(grp) \ 190 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 191 GIC_INTR_CFG_EDGE), \ 192 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 193 GIC_INTR_CFG_EDGE) 194 195 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 196 ARM_SHARED_RAM_BASE, \ 197 ARM_SHARED_RAM_SIZE, \ 198 MT_DEVICE | MT_RW | MT_SECURE) 199 200 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 201 ARM_NS_DRAM1_BASE, \ 202 ARM_NS_DRAM1_SIZE, \ 203 MT_MEMORY | MT_RW | MT_NS) 204 205 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 206 ARM_DRAM2_BASE, \ 207 ARM_DRAM2_SIZE, \ 208 MT_MEMORY | MT_RW | MT_NS) 209 #ifdef SPD_tspd 210 211 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 212 TSP_SEC_MEM_BASE, \ 213 TSP_SEC_MEM_SIZE, \ 214 MT_MEMORY | MT_RW | MT_SECURE) 215 #endif 216 217 #if ARM_BL31_IN_DRAM 218 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 219 BL31_BASE, \ 220 PLAT_ARM_MAX_BL31_SIZE, \ 221 MT_MEMORY | MT_RW | MT_SECURE) 222 #endif 223 224 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 225 ARM_EL3_TZC_DRAM1_BASE, \ 226 ARM_EL3_TZC_DRAM1_SIZE, \ 227 MT_MEMORY | MT_RW | MT_SECURE) 228 229 /* 230 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 231 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 232 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 233 * to be able to access the heap. 234 */ 235 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 236 BL1_RW_BASE, \ 237 BL1_RW_LIMIT - BL1_RW_BASE, \ 238 MT_MEMORY | MT_RW | MT_SECURE) 239 240 /* 241 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 242 * otherwise one region is defined containing both. 243 */ 244 #if SEPARATE_CODE_AND_RODATA 245 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 246 BL_CODE_BASE, \ 247 BL_CODE_END - BL_CODE_BASE, \ 248 MT_CODE | MT_SECURE), \ 249 MAP_REGION_FLAT( \ 250 BL_RO_DATA_BASE, \ 251 BL_RO_DATA_END \ 252 - BL_RO_DATA_BASE, \ 253 MT_RO_DATA | MT_SECURE) 254 #else 255 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 256 BL_CODE_BASE, \ 257 BL_CODE_END - BL_CODE_BASE, \ 258 MT_CODE | MT_SECURE) 259 #endif 260 #if USE_COHERENT_MEM 261 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 262 BL_COHERENT_RAM_BASE, \ 263 BL_COHERENT_RAM_END \ 264 - BL_COHERENT_RAM_BASE, \ 265 MT_DEVICE | MT_RW | MT_SECURE) 266 #endif 267 #if USE_ROMLIB 268 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 269 ROMLIB_RO_BASE, \ 270 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 271 MT_CODE | MT_SECURE) 272 273 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 274 ROMLIB_RW_BASE, \ 275 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 276 MT_MEMORY | MT_RW | MT_SECURE) 277 #endif 278 279 /* 280 * Map mem_protect flash region with read and write permissions 281 */ 282 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 283 V2M_FLASH_BLOCK_SIZE, \ 284 MT_DEVICE | MT_RW | MT_SECURE) 285 286 /* 287 * The max number of regions like RO(code), coherent and data required by 288 * different BL stages which need to be mapped in the MMU. 289 */ 290 #define ARM_BL_REGIONS 5 291 292 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 293 ARM_BL_REGIONS) 294 295 /* Memory mapped Generic timer interfaces */ 296 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 297 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 298 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 299 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 300 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 301 302 #define ARM_CONSOLE_BAUDRATE 115200 303 304 /* Trusted Watchdog constants */ 305 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 306 #define ARM_SP805_TWDG_CLK_HZ 32768 307 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 308 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 309 #define ARM_TWDG_TIMEOUT_SEC 128 310 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 311 ARM_TWDG_TIMEOUT_SEC) 312 313 /****************************************************************************** 314 * Required platform porting definitions common to all ARM standard platforms 315 *****************************************************************************/ 316 317 /* 318 * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for 319 * AArch64 builds 320 */ 321 #ifdef AARCH64 322 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 323 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 324 #else 325 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 326 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 327 #endif 328 329 330 /* 331 * This macro defines the deepest retention state possible. A higher state 332 * id will represent an invalid or a power down state. 333 */ 334 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 335 336 /* 337 * This macro defines the deepest power down states possible. Any state ID 338 * higher than this is invalid. 339 */ 340 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 341 342 /* 343 * Some data must be aligned on the biggest cache line size in the platform. 344 * This is known only to the platform as it might have a combination of 345 * integrated and external caches. 346 */ 347 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 348 349 /* 350 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 351 * and limit. Leave enough space of BL2 meminfo. 352 */ 353 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 354 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 355 356 /******************************************************************************* 357 * BL1 specific defines. 358 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 359 * addresses. 360 ******************************************************************************/ 361 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 362 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 363 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 364 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 365 /* 366 * Put BL1 RW at the top of the Trusted SRAM. 367 */ 368 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 369 ARM_BL_RAM_SIZE - \ 370 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 371 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 372 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 373 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 374 375 #define ROMLIB_RO_BASE BL1_RO_LIMIT 376 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 377 378 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 379 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 380 381 /******************************************************************************* 382 * BL2 specific defines. 383 ******************************************************************************/ 384 #if BL2_AT_EL3 385 /* Put BL2 towards the middle of the Trusted SRAM */ 386 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 387 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 388 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 389 390 #else 391 /* 392 * Put BL2 just below BL1. 393 */ 394 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 395 #define BL2_LIMIT BL1_RW_BASE 396 #endif 397 398 /******************************************************************************* 399 * BL31 specific defines. 400 ******************************************************************************/ 401 #if ARM_BL31_IN_DRAM 402 /* 403 * Put BL31 at the bottom of TZC secured DRAM 404 */ 405 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 406 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 407 PLAT_ARM_MAX_BL31_SIZE) 408 #elif (RESET_TO_BL31) 409 /* 410 * Put BL31_BASE in the middle of the Trusted SRAM. 411 */ 412 #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ 413 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) 414 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 415 #else 416 /* Put BL31 below BL2 in the Trusted SRAM.*/ 417 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 418 - PLAT_ARM_MAX_BL31_SIZE) 419 #define BL31_PROGBITS_LIMIT BL2_BASE 420 /* 421 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 422 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 423 */ 424 #if BL2_AT_EL3 425 #define BL31_LIMIT BL2_BASE 426 #else 427 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 428 #endif 429 #endif 430 431 #if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME 432 /******************************************************************************* 433 * BL32 specific defines for EL3 runtime in AArch32 mode 434 ******************************************************************************/ 435 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 436 /* 437 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding 438 * the page reserved for fw_configs) to BL32 439 */ 440 # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT 441 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 442 # else 443 /* Put BL32 below BL2 in the Trusted SRAM.*/ 444 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 445 - PLAT_ARM_MAX_BL32_SIZE) 446 # define BL32_PROGBITS_LIMIT BL2_BASE 447 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 448 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 449 450 #else 451 /******************************************************************************* 452 * BL32 specific defines for EL3 runtime in AArch64 mode 453 ******************************************************************************/ 454 /* 455 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 456 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 457 * controller. 458 */ 459 # if ENABLE_SPM 460 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 461 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 462 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 463 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 464 ARM_AP_TZC_DRAM1_SIZE) 465 # elif ARM_BL31_IN_DRAM 466 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 467 PLAT_ARM_MAX_BL31_SIZE) 468 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 469 PLAT_ARM_MAX_BL31_SIZE) 470 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 471 PLAT_ARM_MAX_BL31_SIZE) 472 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 473 ARM_AP_TZC_DRAM1_SIZE) 474 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 475 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 476 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 477 # define TSP_PROGBITS_LIMIT BL31_BASE 478 # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT 479 # define BL32_LIMIT BL31_BASE 480 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 481 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 482 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 483 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 484 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 485 + (UL(1) << 21)) 486 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 487 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 488 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 489 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 490 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 491 ARM_AP_TZC_DRAM1_SIZE) 492 # else 493 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 494 # endif 495 #endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */ 496 497 /* 498 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 499 * SPD and no SPM, as they are the only ones that can be used as BL32. 500 */ 501 #if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) 502 # if defined(SPD_none) && !ENABLE_SPM 503 # undef BL32_BASE 504 # endif /* defined(SPD_none) && !ENABLE_SPM */ 505 #endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */ 506 507 /******************************************************************************* 508 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 509 ******************************************************************************/ 510 #define BL2U_BASE BL2_BASE 511 #define BL2U_LIMIT BL2_LIMIT 512 513 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 514 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 515 516 /* 517 * ID of the secure physical generic timer interrupt used by the TSP. 518 */ 519 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 520 521 522 /* 523 * One cache line needed for bakery locks on ARM platforms 524 */ 525 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 526 527 /* Priority levels for ARM platforms */ 528 #define PLAT_RAS_PRI 0x10 529 #define PLAT_SDEI_CRITICAL_PRI 0x60 530 #define PLAT_SDEI_NORMAL_PRI 0x70 531 532 /* ARM platforms use 3 upper bits of secure interrupt priority */ 533 #define ARM_PRI_BITS 3 534 535 /* SGI used for SDEI signalling */ 536 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 537 538 /* ARM SDEI dynamic private event numbers */ 539 #define ARM_SDEI_DP_EVENT_0 1000 540 #define ARM_SDEI_DP_EVENT_1 1001 541 #define ARM_SDEI_DP_EVENT_2 1002 542 543 /* ARM SDEI dynamic shared event numbers */ 544 #define ARM_SDEI_DS_EVENT_0 2000 545 #define ARM_SDEI_DS_EVENT_1 2001 546 #define ARM_SDEI_DS_EVENT_2 2002 547 548 #define ARM_SDEI_PRIVATE_EVENTS \ 549 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 550 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 551 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 552 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 553 554 #define ARM_SDEI_SHARED_EVENTS \ 555 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 556 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 557 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 558 559 #endif /* ARM_DEF_H */ 560