1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <platform_def.h> 12 #include <tbbr_img_def.h> 13 #include <utils_def.h> 14 #include <xlat_tables_defs.h> 15 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define ARM_SYSTEM_COUNT 1 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in ARM platforms encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define ARM_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define ARM_LOCAL_STATE_RET 1 44 /* Local power state for OFF/power-down. Valid for CPU and cluster power 45 domains */ 46 #define ARM_LOCAL_STATE_OFF 2 47 48 /* Memory location options for TSP */ 49 #define ARM_TRUSTED_SRAM_ID 0 50 #define ARM_TRUSTED_DRAM_ID 1 51 #define ARM_DRAM_ID 2 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define ARM_TRUSTED_SRAM_BASE 0x04000000 55 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 56 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 57 58 /* The remaining Trusted SRAM is used to load the BL images */ 59 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 60 ARM_SHARED_RAM_SIZE) 61 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 62 ARM_SHARED_RAM_SIZE) 63 64 /* 65 * The top 16MB of DRAM1 is configured as secure access only using the TZC 66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 68 */ 69 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 70 71 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 72 ARM_DRAM1_SIZE - \ 73 ARM_SCP_TZC_DRAM1_SIZE) 74 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 75 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 76 ARM_SCP_TZC_DRAM1_SIZE - 1) 77 78 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 79 ARM_DRAM1_SIZE - \ 80 ARM_TZC_DRAM1_SIZE) 81 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 82 ARM_SCP_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 84 ARM_AP_TZC_DRAM1_SIZE - 1) 85 86 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 87 #if ARM_CRYPTOCELL_INTEG 88 /* 89 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 90 * This is required by CryptoCell to authenticate BL33 which is loaded 91 * into the Non Secure DDR. 92 */ 93 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 94 #else 95 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 96 #endif 97 98 #ifdef SPD_opteed 99 /* 100 * BL2 needs to map 3.5MB from 512KB offset in TZC_DRAM1 in order to 101 * load/authenticate the trusted os extra image. The first 512KB of TZC_DRAM1 102 * are reserved for trusted os (OPTEE). The extra image loading for OPTEE is 103 * paged image which only include the paging part using virtual memory but 104 * without "init" data. OPTEE will copy the "init" data (from pager image) to 105 * the first 512KB of TZC_DRAM, and then copy the extra image behind the "init" 106 * data. 107 */ 108 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + 0x80000) 109 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x380000 110 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 111 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 112 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 113 MT_MEMORY | MT_RW | MT_SECURE) 114 #endif /* SPD_opteed */ 115 116 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 117 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 118 ARM_TZC_DRAM1_SIZE) 119 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 120 ARM_NS_DRAM1_SIZE - 1) 121 122 #define ARM_DRAM1_BASE ULL(0x80000000) 123 #define ARM_DRAM1_SIZE ULL(0x80000000) 124 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 125 ARM_DRAM1_SIZE - 1) 126 127 #define ARM_DRAM2_BASE ULL(0x880000000) 128 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 129 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 130 ARM_DRAM2_SIZE - 1) 131 132 #define ARM_IRQ_SEC_PHY_TIMER 29 133 134 #define ARM_IRQ_SEC_SGI_0 8 135 #define ARM_IRQ_SEC_SGI_1 9 136 #define ARM_IRQ_SEC_SGI_2 10 137 #define ARM_IRQ_SEC_SGI_3 11 138 #define ARM_IRQ_SEC_SGI_4 12 139 #define ARM_IRQ_SEC_SGI_5 13 140 #define ARM_IRQ_SEC_SGI_6 14 141 #define ARM_IRQ_SEC_SGI_7 15 142 143 /* 144 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 145 * terminology. On a GICv2 system or mode, the lists will be merged and treated 146 * as Group 0 interrupts. 147 */ 148 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 149 ARM_IRQ_SEC_SGI_1, \ 150 ARM_IRQ_SEC_SGI_2, \ 151 ARM_IRQ_SEC_SGI_3, \ 152 ARM_IRQ_SEC_SGI_4, \ 153 ARM_IRQ_SEC_SGI_5, \ 154 ARM_IRQ_SEC_SGI_7 155 156 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 157 ARM_IRQ_SEC_SGI_6 158 159 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 160 ARM_SHARED_RAM_BASE, \ 161 ARM_SHARED_RAM_SIZE, \ 162 MT_DEVICE | MT_RW | MT_SECURE) 163 164 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 165 ARM_NS_DRAM1_BASE, \ 166 ARM_NS_DRAM1_SIZE, \ 167 MT_MEMORY | MT_RW | MT_NS) 168 169 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 170 TSP_SEC_MEM_BASE, \ 171 TSP_SEC_MEM_SIZE, \ 172 MT_MEMORY | MT_RW | MT_SECURE) 173 174 #if ARM_BL31_IN_DRAM 175 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 176 BL31_BASE, \ 177 PLAT_ARM_MAX_BL31_SIZE, \ 178 MT_MEMORY | MT_RW | MT_SECURE) 179 #endif 180 181 /* 182 * The number of regions like RO(code), coherent and data required by 183 * different BL stages which need to be mapped in the MMU. 184 */ 185 #if USE_COHERENT_MEM 186 #define ARM_BL_REGIONS 3 187 #else 188 #define ARM_BL_REGIONS 2 189 #endif 190 191 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 192 ARM_BL_REGIONS) 193 194 /* Memory mapped Generic timer interfaces */ 195 #define ARM_SYS_CNTCTL_BASE 0x2a430000 196 #define ARM_SYS_CNTREAD_BASE 0x2a800000 197 #define ARM_SYS_TIMCTL_BASE 0x2a810000 198 199 #define ARM_CONSOLE_BAUDRATE 115200 200 201 /* Trusted Watchdog constants */ 202 #define ARM_SP805_TWDG_BASE 0x2a490000 203 #define ARM_SP805_TWDG_CLK_HZ 32768 204 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 205 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 206 #define ARM_TWDG_TIMEOUT_SEC 128 207 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 208 ARM_TWDG_TIMEOUT_SEC) 209 210 /****************************************************************************** 211 * Required platform porting definitions common to all ARM standard platforms 212 *****************************************************************************/ 213 214 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 215 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 216 217 /* 218 * This macro defines the deepest retention state possible. A higher state 219 * id will represent an invalid or a power down state. 220 */ 221 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 222 223 /* 224 * This macro defines the deepest power down states possible. Any state ID 225 * higher than this is invalid. 226 */ 227 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 228 229 /* 230 * Some data must be aligned on the biggest cache line size in the platform. 231 * This is known only to the platform as it might have a combination of 232 * integrated and external caches. 233 */ 234 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 235 236 237 /******************************************************************************* 238 * BL1 specific defines. 239 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 240 * addresses. 241 ******************************************************************************/ 242 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 243 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 244 + PLAT_ARM_TRUSTED_ROM_SIZE) 245 /* 246 * Put BL1 RW at the top of the Trusted SRAM. 247 */ 248 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 249 ARM_BL_RAM_SIZE - \ 250 PLAT_ARM_MAX_BL1_RW_SIZE) 251 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 252 253 /******************************************************************************* 254 * BL2 specific defines. 255 ******************************************************************************/ 256 #if ARM_BL31_IN_DRAM || defined(AARCH32) 257 /* 258 * For AArch32 BL31 is not applicable. 259 * For AArch64 BL31 is loaded in the DRAM. 260 * Put BL2 just below BL1. 261 */ 262 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 263 #define BL2_LIMIT BL1_RW_BASE 264 #else 265 /* 266 * Put BL2 just below BL31. 267 */ 268 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 269 #define BL2_LIMIT BL31_BASE 270 #endif 271 272 /******************************************************************************* 273 * BL31 specific defines. 274 ******************************************************************************/ 275 #if ARM_BL31_IN_DRAM 276 /* 277 * Put BL31 at the bottom of TZC secured DRAM 278 */ 279 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 280 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 281 PLAT_ARM_MAX_BL31_SIZE) 282 #else 283 /* 284 * Put BL31 at the top of the Trusted SRAM. 285 */ 286 #define BL31_BASE (ARM_BL_RAM_BASE + \ 287 ARM_BL_RAM_SIZE - \ 288 PLAT_ARM_MAX_BL31_SIZE) 289 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 290 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 291 #endif 292 293 /******************************************************************************* 294 * BL32 specific defines. 295 ******************************************************************************/ 296 /* 297 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 298 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 299 * controller. 300 */ 301 #if ARM_BL31_IN_DRAM 302 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 303 PLAT_ARM_MAX_BL31_SIZE) 304 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 305 PLAT_ARM_MAX_BL31_SIZE) 306 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 307 PLAT_ARM_MAX_BL31_SIZE) 308 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 309 ARM_AP_TZC_DRAM1_SIZE) 310 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 311 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 312 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 313 # define TSP_PROGBITS_LIMIT BL2_BASE 314 # define BL32_BASE ARM_BL_RAM_BASE 315 # define BL32_LIMIT BL31_BASE 316 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 317 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 318 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 319 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 320 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 321 + (1 << 21)) 322 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 323 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 324 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 325 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 326 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 327 ARM_AP_TZC_DRAM1_SIZE) 328 #else 329 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 330 #endif 331 332 /* BL32 is mandatory in AArch32 */ 333 #ifndef AARCH32 334 #ifdef SPD_none 335 #undef BL32_BASE 336 #endif /* SPD_none */ 337 #endif 338 339 /******************************************************************************* 340 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 341 ******************************************************************************/ 342 #define BL2U_BASE BL2_BASE 343 #if ARM_BL31_IN_DRAM || defined(AARCH32) 344 /* 345 * For AArch32 BL31 is not applicable. 346 * For AArch64 BL31 is loaded in the DRAM. 347 * BL2U extends up to BL1. 348 */ 349 #define BL2U_LIMIT BL1_RW_BASE 350 #else 351 /* BL2U extends up to BL31. */ 352 #define BL2U_LIMIT BL31_BASE 353 #endif 354 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 355 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 356 357 /* 358 * ID of the secure physical generic timer interrupt used by the TSP. 359 */ 360 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 361 362 363 /* 364 * One cache line needed for bakery locks on ARM platforms 365 */ 366 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 367 368 369 #endif /* __ARM_DEF_H__ */ 370