1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __ARM_DEF_H__ 31 #define __ARM_DEF_H__ 32 33 #include <arch.h> 34 #include <common_def.h> 35 #include <platform_def.h> 36 #include <tbbr_img_def.h> 37 #include <xlat_tables.h> 38 39 40 /****************************************************************************** 41 * Definitions common to all ARM standard platforms 42 *****************************************************************************/ 43 44 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 45 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 46 47 #define ARM_CLUSTER_COUNT 2ull 48 49 #define ARM_CACHE_WRITEBACK_SHIFT 6 50 51 /* 52 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 53 * power levels have a 1:1 mapping with the MPIDR affinity levels. 54 */ 55 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 56 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 57 58 /* 59 * Macros for local power states in ARM platforms encoded by State-ID field 60 * within the power-state parameter. 61 */ 62 /* Local power state for power domains in Run state. */ 63 #define ARM_LOCAL_STATE_RUN 0 64 /* Local power state for retention. Valid only for CPU power domains */ 65 #define ARM_LOCAL_STATE_RET 1 66 /* Local power state for OFF/power-down. Valid for CPU and cluster power 67 domains */ 68 #define ARM_LOCAL_STATE_OFF 2 69 70 /* Memory location options for TSP */ 71 #define ARM_TRUSTED_SRAM_ID 0 72 #define ARM_TRUSTED_DRAM_ID 1 73 #define ARM_DRAM_ID 2 74 75 /* The first 4KB of Trusted SRAM are used as shared memory */ 76 #define ARM_TRUSTED_SRAM_BASE 0x04000000 77 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 78 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 79 80 /* The remaining Trusted SRAM is used to load the BL images */ 81 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 82 ARM_SHARED_RAM_SIZE) 83 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 84 ARM_SHARED_RAM_SIZE) 85 86 /* 87 * The top 16MB of DRAM1 is configured as secure access only using the TZC 88 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 89 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 90 */ 91 #define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) 92 93 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 94 ARM_DRAM1_SIZE - \ 95 ARM_SCP_TZC_DRAM1_SIZE) 96 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 97 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 98 ARM_SCP_TZC_DRAM1_SIZE - 1) 99 100 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 101 ARM_DRAM1_SIZE - \ 102 ARM_TZC_DRAM1_SIZE) 103 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 104 ARM_SCP_TZC_DRAM1_SIZE) 105 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 106 ARM_AP_TZC_DRAM1_SIZE - 1) 107 108 109 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 110 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 111 ARM_TZC_DRAM1_SIZE) 112 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 113 ARM_NS_DRAM1_SIZE - 1) 114 115 #define ARM_DRAM1_BASE MAKE_ULL(0x80000000) 116 #define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) 117 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 118 ARM_DRAM1_SIZE - 1) 119 120 #define ARM_DRAM2_BASE MAKE_ULL(0x880000000) 121 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 122 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 123 ARM_DRAM2_SIZE - 1) 124 125 #define ARM_IRQ_SEC_PHY_TIMER 29 126 127 #define ARM_IRQ_SEC_SGI_0 8 128 #define ARM_IRQ_SEC_SGI_1 9 129 #define ARM_IRQ_SEC_SGI_2 10 130 #define ARM_IRQ_SEC_SGI_3 11 131 #define ARM_IRQ_SEC_SGI_4 12 132 #define ARM_IRQ_SEC_SGI_5 13 133 #define ARM_IRQ_SEC_SGI_6 14 134 #define ARM_IRQ_SEC_SGI_7 15 135 136 #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ 137 MT_MEMORY : MT_DEVICE) \ 138 | MT_RW | MT_SECURE) 139 140 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 141 ARM_SHARED_RAM_BASE, \ 142 ARM_SHARED_RAM_SIZE, \ 143 ARM_SHARED_RAM_ATTR) 144 145 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 146 ARM_NS_DRAM1_BASE, \ 147 ARM_NS_DRAM1_SIZE, \ 148 MT_MEMORY | MT_RW | MT_NS) 149 150 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 151 TSP_SEC_MEM_BASE, \ 152 TSP_SEC_MEM_SIZE, \ 153 MT_MEMORY | MT_RW | MT_SECURE) 154 155 156 /* 157 * The number of regions like RO(code), coherent and data required by 158 * different BL stages which need to be mapped in the MMU. 159 */ 160 #if USE_COHERENT_MEM 161 #define ARM_BL_REGIONS 3 162 #else 163 #define ARM_BL_REGIONS 2 164 #endif 165 166 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 167 ARM_BL_REGIONS) 168 169 /* Memory mapped Generic timer interfaces */ 170 #define ARM_SYS_CNTCTL_BASE 0x2a430000 171 #define ARM_SYS_CNTREAD_BASE 0x2a800000 172 #define ARM_SYS_TIMCTL_BASE 0x2a810000 173 174 #define ARM_CONSOLE_BAUDRATE 115200 175 176 /* TZC related constants */ 177 #define ARM_TZC_BASE 0x2a4a0000 178 179 180 /****************************************************************************** 181 * Required platform porting definitions common to all ARM standard platforms 182 *****************************************************************************/ 183 184 #define ADDR_SPACE_SIZE (1ull << 32) 185 186 #define PLAT_NUM_PWR_DOMAINS (ARM_CLUSTER_COUNT + \ 187 PLATFORM_CORE_COUNT) 188 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 189 190 /* 191 * This macro defines the deepest retention state possible. A higher state 192 * id will represent an invalid or a power down state. 193 */ 194 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 195 196 /* 197 * This macro defines the deepest power down states possible. Any state ID 198 * higher than this is invalid. 199 */ 200 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 201 202 203 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ 204 PLAT_ARM_CLUSTER1_CORE_COUNT) 205 206 /* 207 * Some data must be aligned on the biggest cache line size in the platform. 208 * This is known only to the platform as it might have a combination of 209 * integrated and external caches. 210 */ 211 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 212 213 #if !USE_COHERENT_MEM 214 /* 215 * Size of the per-cpu data in bytes that should be reserved in the generic 216 * per-cpu data structure for the ARM platform port. 217 */ 218 #define PLAT_PCPU_DATA_SIZE 2 219 #endif 220 221 222 /******************************************************************************* 223 * BL1 specific defines. 224 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 225 * addresses. 226 ******************************************************************************/ 227 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 228 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 229 + PLAT_ARM_TRUSTED_ROM_SIZE) 230 /* 231 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 232 * the current BL1 RW debug size plus a little space for growth. 233 */ 234 #if TRUSTED_BOARD_BOOT 235 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 236 ARM_BL_RAM_SIZE - \ 237 0x9000) 238 #else 239 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 240 ARM_BL_RAM_SIZE - \ 241 0x6000) 242 #endif 243 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 244 245 /******************************************************************************* 246 * BL2 specific defines. 247 ******************************************************************************/ 248 /* 249 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 250 * size plus a little space for growth. 251 */ 252 #if TRUSTED_BOARD_BOOT 253 #define BL2_BASE (BL31_BASE - 0x1D000) 254 #else 255 #define BL2_BASE (BL31_BASE - 0xC000) 256 #endif 257 #define BL2_LIMIT BL31_BASE 258 259 /******************************************************************************* 260 * BL3-1 specific defines. 261 ******************************************************************************/ 262 /* 263 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 264 * current BL3-1 debug size plus a little space for growth. 265 */ 266 #define BL31_BASE (ARM_BL_RAM_BASE + \ 267 ARM_BL_RAM_SIZE - \ 268 0x1D000) 269 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 270 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 271 272 /******************************************************************************* 273 * BL3-2 specific defines. 274 ******************************************************************************/ 275 /* 276 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 277 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 278 * controller. 279 */ 280 #if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 281 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 282 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 283 # define TSP_PROGBITS_LIMIT BL2_BASE 284 # define BL32_BASE ARM_BL_RAM_BASE 285 # define BL32_LIMIT BL31_BASE 286 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 287 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 288 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 289 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 290 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 291 + (1 << 21)) 292 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 293 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 294 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 295 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 296 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 297 ARM_AP_TZC_DRAM1_SIZE) 298 #else 299 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 300 #endif 301 302 /* 303 * ID of the secure physical generic timer interrupt used by the TSP. 304 */ 305 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 306 307 308 #endif /* __ARM_DEF_H__ */ 309