1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __ARM_DEF_H__ 31 #define __ARM_DEF_H__ 32 33 #include <common_def.h> 34 #include <platform_def.h> 35 #include <xlat_tables.h> 36 37 38 /****************************************************************************** 39 * Definitions common to all ARM standard platforms 40 *****************************************************************************/ 41 42 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 43 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 44 45 #define ARM_CLUSTER_COUNT 2ull 46 47 #define ARM_CACHE_WRITEBACK_SHIFT 6 48 49 /* Memory location options for TSP */ 50 #define ARM_TRUSTED_SRAM_ID 0 51 #define ARM_TRUSTED_DRAM_ID 1 52 #define ARM_DRAM_ID 2 53 54 /* The first 4KB of Trusted SRAM are used as shared memory */ 55 #define ARM_TRUSTED_SRAM_BASE 0x04000000 56 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 57 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 58 59 /* The remaining Trusted SRAM is used to load the BL images */ 60 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 61 ARM_SHARED_RAM_SIZE) 62 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 63 ARM_SHARED_RAM_SIZE) 64 65 /* 66 * The top 16MB of DRAM1 is configured as secure access only using the TZC 67 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 68 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 69 */ 70 #define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) 71 72 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 73 ARM_DRAM1_SIZE - \ 74 ARM_SCP_TZC_DRAM1_SIZE) 75 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 76 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 77 ARM_SCP_TZC_DRAM1_SIZE - 1) 78 79 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 80 ARM_DRAM1_SIZE - \ 81 ARM_TZC_DRAM1_SIZE) 82 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 83 ARM_SCP_TZC_DRAM1_SIZE) 84 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 85 ARM_AP_TZC_DRAM1_SIZE - 1) 86 87 88 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 89 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 90 ARM_TZC_DRAM1_SIZE) 91 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 92 ARM_NS_DRAM1_SIZE - 1) 93 94 #define ARM_DRAM1_BASE MAKE_ULL(0x80000000) 95 #define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) 96 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 97 ARM_DRAM1_SIZE - 1) 98 99 #define ARM_DRAM2_BASE MAKE_ULL(0x880000000) 100 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 101 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 102 ARM_DRAM2_SIZE - 1) 103 104 #define ARM_IRQ_SEC_PHY_TIMER 29 105 106 #define ARM_IRQ_SEC_SGI_0 8 107 #define ARM_IRQ_SEC_SGI_1 9 108 #define ARM_IRQ_SEC_SGI_2 10 109 #define ARM_IRQ_SEC_SGI_3 11 110 #define ARM_IRQ_SEC_SGI_4 12 111 #define ARM_IRQ_SEC_SGI_5 13 112 #define ARM_IRQ_SEC_SGI_6 14 113 #define ARM_IRQ_SEC_SGI_7 15 114 115 #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ 116 MT_MEMORY : MT_DEVICE) \ 117 | MT_RW | MT_SECURE) 118 119 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 120 ARM_SHARED_RAM_BASE, \ 121 ARM_SHARED_RAM_SIZE, \ 122 ARM_SHARED_RAM_ATTR) 123 124 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 125 ARM_NS_DRAM1_BASE, \ 126 ARM_NS_DRAM1_SIZE, \ 127 MT_MEMORY | MT_RW | MT_NS) 128 129 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 130 TSP_SEC_MEM_BASE, \ 131 TSP_SEC_MEM_SIZE, \ 132 MT_MEMORY | MT_RW | MT_SECURE) 133 134 135 /* 136 * The number of regions like RO(code), coherent and data required by 137 * different BL stages which need to be mapped in the MMU. 138 */ 139 #if USE_COHERENT_MEM 140 #define ARM_BL_REGIONS 3 141 #else 142 #define ARM_BL_REGIONS 2 143 #endif 144 145 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 146 ARM_BL_REGIONS) 147 148 /* Memory mapped Generic timer interfaces */ 149 #define ARM_SYS_CNTCTL_BASE 0x2a430000 150 #define ARM_SYS_CNTREAD_BASE 0x2a800000 151 #define ARM_SYS_TIMCTL_BASE 0x2a810000 152 153 #define ARM_CONSOLE_BAUDRATE 115200 154 155 /* TZC related constants */ 156 #define ARM_TZC_BASE 0x2a4a0000 157 158 159 /****************************************************************************** 160 * Required platform porting definitions common to all ARM standard platforms 161 *****************************************************************************/ 162 163 #define ADDR_SPACE_SIZE (1ull << 32) 164 165 #define PLATFORM_NUM_AFFS (ARM_CLUSTER_COUNT + \ 166 PLATFORM_CORE_COUNT) 167 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 168 169 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ 170 PLAT_ARM_CLUSTER1_CORE_COUNT) 171 172 /* 173 * Some data must be aligned on the biggest cache line size in the platform. 174 * This is known only to the platform as it might have a combination of 175 * integrated and external caches. 176 */ 177 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 178 179 #if !USE_COHERENT_MEM 180 /* 181 * Size of the per-cpu data in bytes that should be reserved in the generic 182 * per-cpu data structure for the ARM platform port. 183 */ 184 #define PLAT_PCPU_DATA_SIZE 2 185 #endif 186 187 188 /******************************************************************************* 189 * BL1 specific defines. 190 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 191 * addresses. 192 ******************************************************************************/ 193 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 194 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 195 + PLAT_ARM_TRUSTED_ROM_SIZE) 196 /* 197 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 198 * the current BL1 RW debug size plus a little space for growth. 199 */ 200 #if TRUSTED_BOARD_BOOT 201 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 202 ARM_BL_RAM_SIZE - \ 203 0x8000) 204 #else 205 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 206 ARM_BL_RAM_SIZE - \ 207 0x6000) 208 #endif 209 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 210 211 /******************************************************************************* 212 * BL2 specific defines. 213 ******************************************************************************/ 214 /* 215 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 216 * size plus a little space for growth. 217 */ 218 #if TRUSTED_BOARD_BOOT 219 #define BL2_BASE (BL31_BASE - 0x1C000) 220 #else 221 #define BL2_BASE (BL31_BASE - 0xC000) 222 #endif 223 #define BL2_LIMIT BL31_BASE 224 225 /******************************************************************************* 226 * BL3-1 specific defines. 227 ******************************************************************************/ 228 /* 229 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 230 * current BL3-1 debug size plus a little space for growth. 231 */ 232 #define BL31_BASE (ARM_BL_RAM_BASE + \ 233 ARM_BL_RAM_SIZE - \ 234 0x1D000) 235 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 236 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 237 238 /******************************************************************************* 239 * BL3-2 specific defines. 240 ******************************************************************************/ 241 /* 242 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 243 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 244 * controller. 245 */ 246 #if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 247 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 248 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 249 # define TSP_PROGBITS_LIMIT BL2_BASE 250 # define BL32_BASE ARM_BL_RAM_BASE 251 # define BL32_LIMIT BL31_BASE 252 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 253 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 254 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 255 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 256 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 257 + (1 << 21)) 258 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 259 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 260 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 261 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 262 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 263 ARM_AP_TZC_DRAM1_SIZE) 264 #else 265 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 266 #endif 267 268 /* 269 * ID of the secure physical generic timer interrupt used by the TSP. 270 */ 271 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 272 273 274 #endif /* __ARM_DEF_H__ */ 275