1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef __ARM_DEF_H__ 7 #define __ARM_DEF_H__ 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <platform_def.h> 12 #include <tbbr_img_def.h> 13 #include <utils_def.h> 14 #include <xlat_tables_defs.h> 15 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* Special value used to verify platform parameters from BL2 to BL31 */ 22 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 23 24 #define ARM_SYSTEM_COUNT 1 25 26 #define ARM_CACHE_WRITEBACK_SHIFT 6 27 28 /* 29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 30 * power levels have a 1:1 mapping with the MPIDR affinity levels. 31 */ 32 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 33 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 34 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 35 36 /* 37 * Macros for local power states in ARM platforms encoded by State-ID field 38 * within the power-state parameter. 39 */ 40 /* Local power state for power domains in Run state. */ 41 #define ARM_LOCAL_STATE_RUN 0 42 /* Local power state for retention. Valid only for CPU power domains */ 43 #define ARM_LOCAL_STATE_RET 1 44 /* Local power state for OFF/power-down. Valid for CPU and cluster power 45 domains */ 46 #define ARM_LOCAL_STATE_OFF 2 47 48 /* Memory location options for TSP */ 49 #define ARM_TRUSTED_SRAM_ID 0 50 #define ARM_TRUSTED_DRAM_ID 1 51 #define ARM_DRAM_ID 2 52 53 /* The first 4KB of Trusted SRAM are used as shared memory */ 54 #define ARM_TRUSTED_SRAM_BASE 0x04000000 55 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 56 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 57 58 /* The remaining Trusted SRAM is used to load the BL images */ 59 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 60 ARM_SHARED_RAM_SIZE) 61 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 62 ARM_SHARED_RAM_SIZE) 63 64 /* 65 * The top 16MB of DRAM1 is configured as secure access only using the TZC 66 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 67 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 68 */ 69 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 70 71 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 72 ARM_DRAM1_SIZE - \ 73 ARM_SCP_TZC_DRAM1_SIZE) 74 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 75 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 76 ARM_SCP_TZC_DRAM1_SIZE - 1) 77 78 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 79 ARM_DRAM1_SIZE - \ 80 ARM_TZC_DRAM1_SIZE) 81 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 82 ARM_SCP_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 84 ARM_AP_TZC_DRAM1_SIZE - 1) 85 86 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 87 #if ARM_CRYPTOCELL_INTEG 88 /* 89 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 90 * This is required by CryptoCell to authenticate BL33 which is loaded 91 * into the Non Secure DDR. 92 */ 93 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 94 #else 95 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 96 #endif 97 98 99 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 100 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 101 ARM_TZC_DRAM1_SIZE) 102 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 103 ARM_NS_DRAM1_SIZE - 1) 104 105 #define ARM_DRAM1_BASE ULL(0x80000000) 106 #define ARM_DRAM1_SIZE ULL(0x80000000) 107 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 108 ARM_DRAM1_SIZE - 1) 109 110 #define ARM_DRAM2_BASE ULL(0x880000000) 111 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 112 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 113 ARM_DRAM2_SIZE - 1) 114 115 #define ARM_IRQ_SEC_PHY_TIMER 29 116 117 #define ARM_IRQ_SEC_SGI_0 8 118 #define ARM_IRQ_SEC_SGI_1 9 119 #define ARM_IRQ_SEC_SGI_2 10 120 #define ARM_IRQ_SEC_SGI_3 11 121 #define ARM_IRQ_SEC_SGI_4 12 122 #define ARM_IRQ_SEC_SGI_5 13 123 #define ARM_IRQ_SEC_SGI_6 14 124 #define ARM_IRQ_SEC_SGI_7 15 125 126 /* 127 * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3 128 * terminology. On a GICv2 system or mode, the lists will be merged and treated 129 * as Group 0 interrupts. 130 */ 131 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 132 ARM_IRQ_SEC_SGI_1, \ 133 ARM_IRQ_SEC_SGI_2, \ 134 ARM_IRQ_SEC_SGI_3, \ 135 ARM_IRQ_SEC_SGI_4, \ 136 ARM_IRQ_SEC_SGI_5, \ 137 ARM_IRQ_SEC_SGI_7 138 139 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 140 ARM_IRQ_SEC_SGI_6 141 142 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 143 ARM_SHARED_RAM_BASE, \ 144 ARM_SHARED_RAM_SIZE, \ 145 MT_DEVICE | MT_RW | MT_SECURE) 146 147 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 148 ARM_NS_DRAM1_BASE, \ 149 ARM_NS_DRAM1_SIZE, \ 150 MT_MEMORY | MT_RW | MT_NS) 151 152 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 153 TSP_SEC_MEM_BASE, \ 154 TSP_SEC_MEM_SIZE, \ 155 MT_MEMORY | MT_RW | MT_SECURE) 156 157 #if ARM_BL31_IN_DRAM 158 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 159 BL31_BASE, \ 160 PLAT_ARM_MAX_BL31_SIZE, \ 161 MT_MEMORY | MT_RW | MT_SECURE) 162 #endif 163 164 /* 165 * The number of regions like RO(code), coherent and data required by 166 * different BL stages which need to be mapped in the MMU. 167 */ 168 #if USE_COHERENT_MEM 169 #define ARM_BL_REGIONS 3 170 #else 171 #define ARM_BL_REGIONS 2 172 #endif 173 174 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 175 ARM_BL_REGIONS) 176 177 /* Memory mapped Generic timer interfaces */ 178 #define ARM_SYS_CNTCTL_BASE 0x2a430000 179 #define ARM_SYS_CNTREAD_BASE 0x2a800000 180 #define ARM_SYS_TIMCTL_BASE 0x2a810000 181 182 #define ARM_CONSOLE_BAUDRATE 115200 183 184 /* Trusted Watchdog constants */ 185 #define ARM_SP805_TWDG_BASE 0x2a490000 186 #define ARM_SP805_TWDG_CLK_HZ 32768 187 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 188 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 189 #define ARM_TWDG_TIMEOUT_SEC 128 190 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 191 ARM_TWDG_TIMEOUT_SEC) 192 193 /****************************************************************************** 194 * Required platform porting definitions common to all ARM standard platforms 195 *****************************************************************************/ 196 197 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 198 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 199 200 /* 201 * This macro defines the deepest retention state possible. A higher state 202 * id will represent an invalid or a power down state. 203 */ 204 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 205 206 /* 207 * This macro defines the deepest power down states possible. Any state ID 208 * higher than this is invalid. 209 */ 210 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 211 212 /* 213 * Some data must be aligned on the biggest cache line size in the platform. 214 * This is known only to the platform as it might have a combination of 215 * integrated and external caches. 216 */ 217 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 218 219 220 /******************************************************************************* 221 * BL1 specific defines. 222 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 223 * addresses. 224 ******************************************************************************/ 225 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 226 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 227 + PLAT_ARM_TRUSTED_ROM_SIZE) 228 /* 229 * Put BL1 RW at the top of the Trusted SRAM. 230 */ 231 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 232 ARM_BL_RAM_SIZE - \ 233 PLAT_ARM_MAX_BL1_RW_SIZE) 234 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 235 236 /******************************************************************************* 237 * BL2 specific defines. 238 ******************************************************************************/ 239 #if ARM_BL31_IN_DRAM || defined(AARCH32) 240 /* 241 * For AArch32 BL31 is not applicable. 242 * For AArch64 BL31 is loaded in the DRAM. 243 * Put BL2 just below BL1. 244 */ 245 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 246 #define BL2_LIMIT BL1_RW_BASE 247 #else 248 /* 249 * Put BL2 just below BL31. 250 */ 251 #define BL2_BASE (BL31_BASE - PLAT_ARM_MAX_BL2_SIZE) 252 #define BL2_LIMIT BL31_BASE 253 #endif 254 255 /******************************************************************************* 256 * BL31 specific defines. 257 ******************************************************************************/ 258 #if ARM_BL31_IN_DRAM 259 /* 260 * Put BL31 at the bottom of TZC secured DRAM 261 */ 262 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 263 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 264 PLAT_ARM_MAX_BL31_SIZE) 265 #else 266 /* 267 * Put BL31 at the top of the Trusted SRAM. 268 */ 269 #define BL31_BASE (ARM_BL_RAM_BASE + \ 270 ARM_BL_RAM_SIZE - \ 271 PLAT_ARM_MAX_BL31_SIZE) 272 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 273 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 274 #endif 275 276 /******************************************************************************* 277 * BL32 specific defines. 278 ******************************************************************************/ 279 /* 280 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 281 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 282 * controller. 283 */ 284 #if ARM_BL31_IN_DRAM 285 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 286 PLAT_ARM_MAX_BL31_SIZE) 287 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 288 PLAT_ARM_MAX_BL31_SIZE) 289 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 290 PLAT_ARM_MAX_BL31_SIZE) 291 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 292 ARM_AP_TZC_DRAM1_SIZE) 293 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 294 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 295 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 296 # define TSP_PROGBITS_LIMIT BL2_BASE 297 # define BL32_BASE ARM_BL_RAM_BASE 298 # define BL32_LIMIT BL31_BASE 299 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 300 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 301 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 302 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 303 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 304 + (1 << 21)) 305 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 306 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 307 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 308 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 309 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 310 ARM_AP_TZC_DRAM1_SIZE) 311 #else 312 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 313 #endif 314 315 /* BL32 is mandatory in AArch32 */ 316 #ifndef AARCH32 317 #ifdef SPD_none 318 #undef BL32_BASE 319 #endif /* SPD_none */ 320 #endif 321 322 /******************************************************************************* 323 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 324 ******************************************************************************/ 325 #define BL2U_BASE BL2_BASE 326 #if ARM_BL31_IN_DRAM || defined(AARCH32) 327 /* 328 * For AArch32 BL31 is not applicable. 329 * For AArch64 BL31 is loaded in the DRAM. 330 * BL2U extends up to BL1. 331 */ 332 #define BL2U_LIMIT BL1_RW_BASE 333 #else 334 /* BL2U extends up to BL31. */ 335 #define BL2U_LIMIT BL31_BASE 336 #endif 337 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 338 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 339 340 /* 341 * ID of the secure physical generic timer interrupt used by the TSP. 342 */ 343 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 344 345 346 /* 347 * One cache line needed for bakery locks on ARM platforms 348 */ 349 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 350 351 352 #endif /* __ARM_DEF_H__ */ 353