1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __ARM_DEF_H__ 31 #define __ARM_DEF_H__ 32 33 #include <arch.h> 34 #include <common_def.h> 35 #include <platform_def.h> 36 #include <tbbr_img_def.h> 37 #include <xlat_tables.h> 38 39 40 /****************************************************************************** 41 * Definitions common to all ARM standard platforms 42 *****************************************************************************/ 43 44 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 45 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 46 47 #define ARM_CLUSTER_COUNT 2 48 #define ARM_SYSTEM_COUNT 1 49 50 #define ARM_CACHE_WRITEBACK_SHIFT 6 51 52 /* 53 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 54 * power levels have a 1:1 mapping with the MPIDR affinity levels. 55 */ 56 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 57 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 58 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 59 60 /* 61 * Macros for local power states in ARM platforms encoded by State-ID field 62 * within the power-state parameter. 63 */ 64 /* Local power state for power domains in Run state. */ 65 #define ARM_LOCAL_STATE_RUN 0 66 /* Local power state for retention. Valid only for CPU power domains */ 67 #define ARM_LOCAL_STATE_RET 1 68 /* Local power state for OFF/power-down. Valid for CPU and cluster power 69 domains */ 70 #define ARM_LOCAL_STATE_OFF 2 71 72 /* Memory location options for TSP */ 73 #define ARM_TRUSTED_SRAM_ID 0 74 #define ARM_TRUSTED_DRAM_ID 1 75 #define ARM_DRAM_ID 2 76 77 /* The first 4KB of Trusted SRAM are used as shared memory */ 78 #define ARM_TRUSTED_SRAM_BASE 0x04000000 79 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 80 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 81 82 /* The remaining Trusted SRAM is used to load the BL images */ 83 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 84 ARM_SHARED_RAM_SIZE) 85 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 86 ARM_SHARED_RAM_SIZE) 87 88 /* 89 * The top 16MB of DRAM1 is configured as secure access only using the TZC 90 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 91 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 92 */ 93 #define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) 94 95 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 96 ARM_DRAM1_SIZE - \ 97 ARM_SCP_TZC_DRAM1_SIZE) 98 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 99 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 100 ARM_SCP_TZC_DRAM1_SIZE - 1) 101 102 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 103 ARM_DRAM1_SIZE - \ 104 ARM_TZC_DRAM1_SIZE) 105 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 106 ARM_SCP_TZC_DRAM1_SIZE) 107 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 108 ARM_AP_TZC_DRAM1_SIZE - 1) 109 110 111 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 112 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 113 ARM_TZC_DRAM1_SIZE) 114 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 115 ARM_NS_DRAM1_SIZE - 1) 116 117 #define ARM_DRAM1_BASE MAKE_ULL(0x80000000) 118 #define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) 119 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 120 ARM_DRAM1_SIZE - 1) 121 122 #define ARM_DRAM2_BASE MAKE_ULL(0x880000000) 123 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 124 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 125 ARM_DRAM2_SIZE - 1) 126 127 #define ARM_IRQ_SEC_PHY_TIMER 29 128 129 #define ARM_IRQ_SEC_SGI_0 8 130 #define ARM_IRQ_SEC_SGI_1 9 131 #define ARM_IRQ_SEC_SGI_2 10 132 #define ARM_IRQ_SEC_SGI_3 11 133 #define ARM_IRQ_SEC_SGI_4 12 134 #define ARM_IRQ_SEC_SGI_5 13 135 #define ARM_IRQ_SEC_SGI_6 14 136 #define ARM_IRQ_SEC_SGI_7 15 137 138 #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ 139 MT_MEMORY : MT_DEVICE) \ 140 | MT_RW | MT_SECURE) 141 142 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 143 ARM_SHARED_RAM_BASE, \ 144 ARM_SHARED_RAM_SIZE, \ 145 ARM_SHARED_RAM_ATTR) 146 147 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 148 ARM_NS_DRAM1_BASE, \ 149 ARM_NS_DRAM1_SIZE, \ 150 MT_MEMORY | MT_RW | MT_NS) 151 152 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 153 TSP_SEC_MEM_BASE, \ 154 TSP_SEC_MEM_SIZE, \ 155 MT_MEMORY | MT_RW | MT_SECURE) 156 157 158 /* 159 * The number of regions like RO(code), coherent and data required by 160 * different BL stages which need to be mapped in the MMU. 161 */ 162 #if USE_COHERENT_MEM 163 #define ARM_BL_REGIONS 3 164 #else 165 #define ARM_BL_REGIONS 2 166 #endif 167 168 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 169 ARM_BL_REGIONS) 170 171 /* Memory mapped Generic timer interfaces */ 172 #define ARM_SYS_CNTCTL_BASE 0x2a430000 173 #define ARM_SYS_CNTREAD_BASE 0x2a800000 174 #define ARM_SYS_TIMCTL_BASE 0x2a810000 175 176 #define ARM_CONSOLE_BAUDRATE 115200 177 178 /****************************************************************************** 179 * Required platform porting definitions common to all ARM standard platforms 180 *****************************************************************************/ 181 182 #define ADDR_SPACE_SIZE (1ull << 32) 183 184 /* 185 * This macro defines the deepest retention state possible. A higher state 186 * id will represent an invalid or a power down state. 187 */ 188 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 189 190 /* 191 * This macro defines the deepest power down states possible. Any state ID 192 * higher than this is invalid. 193 */ 194 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 195 196 197 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ 198 PLAT_ARM_CLUSTER1_CORE_COUNT) 199 200 /* 201 * Some data must be aligned on the biggest cache line size in the platform. 202 * This is known only to the platform as it might have a combination of 203 * integrated and external caches. 204 */ 205 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 206 207 208 /******************************************************************************* 209 * BL1 specific defines. 210 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 211 * addresses. 212 ******************************************************************************/ 213 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 214 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 215 + PLAT_ARM_TRUSTED_ROM_SIZE) 216 /* 217 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 218 * the current BL1 RW debug size plus a little space for growth. 219 */ 220 #if TRUSTED_BOARD_BOOT 221 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 222 ARM_BL_RAM_SIZE - \ 223 0x9000) 224 #else 225 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 226 ARM_BL_RAM_SIZE - \ 227 0x6000) 228 #endif 229 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 230 231 /******************************************************************************* 232 * BL2 specific defines. 233 ******************************************************************************/ 234 /* 235 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 236 * size plus a little space for growth. 237 */ 238 #if TRUSTED_BOARD_BOOT 239 #define BL2_BASE (BL31_BASE - 0x1D000) 240 #else 241 #define BL2_BASE (BL31_BASE - 0xC000) 242 #endif 243 #define BL2_LIMIT BL31_BASE 244 245 /******************************************************************************* 246 * BL3-1 specific defines. 247 ******************************************************************************/ 248 /* 249 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 250 * current BL3-1 debug size plus a little space for growth. 251 */ 252 #define BL31_BASE (ARM_BL_RAM_BASE + \ 253 ARM_BL_RAM_SIZE - \ 254 0x1D000) 255 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 256 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 257 258 /******************************************************************************* 259 * BL3-2 specific defines. 260 ******************************************************************************/ 261 /* 262 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 263 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 264 * controller. 265 */ 266 #if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 267 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 268 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 269 # define TSP_PROGBITS_LIMIT BL2_BASE 270 # define BL32_BASE ARM_BL_RAM_BASE 271 # define BL32_LIMIT BL31_BASE 272 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 273 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 274 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 275 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 276 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 277 + (1 << 21)) 278 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 279 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 280 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 281 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 282 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 283 ARM_AP_TZC_DRAM1_SIZE) 284 #else 285 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 286 #endif 287 288 /* 289 * ID of the secure physical generic timer interrupt used by the TSP. 290 */ 291 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 292 293 294 /* 295 * One cache line needed for bakery locks on ARM platforms 296 */ 297 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 298 299 300 #endif /* __ARM_DEF_H__ */ 301