1 /* 2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/common/common_def.h> 16 17 /****************************************************************************** 18 * Definitions common to all ARM standard platforms 19 *****************************************************************************/ 20 21 /* 22 * Root of trust key hash lengths 23 */ 24 #define ARM_ROTPK_HEADER_LEN 19 25 #define ARM_ROTPK_HASH_LEN 32 26 27 /* Special value used to verify platform parameters from BL2 to BL31 */ 28 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 29 30 #define ARM_SYSTEM_COUNT U(1) 31 32 #define ARM_CACHE_WRITEBACK_SHIFT 6 33 34 /* 35 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 36 * power levels have a 1:1 mapping with the MPIDR affinity levels. 37 */ 38 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 39 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 40 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 41 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 42 43 /* 44 * Macros for local power states in ARM platforms encoded by State-ID field 45 * within the power-state parameter. 46 */ 47 /* Local power state for power domains in Run state. */ 48 #define ARM_LOCAL_STATE_RUN U(0) 49 /* Local power state for retention. Valid only for CPU power domains */ 50 #define ARM_LOCAL_STATE_RET U(1) 51 /* Local power state for OFF/power-down. Valid for CPU and cluster power 52 domains */ 53 #define ARM_LOCAL_STATE_OFF U(2) 54 55 /* Memory location options for TSP */ 56 #define ARM_TRUSTED_SRAM_ID 0 57 #define ARM_TRUSTED_DRAM_ID 1 58 #define ARM_DRAM_ID 2 59 60 /* The first 4KB of Trusted SRAM are used as shared memory */ 61 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 62 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 63 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 64 65 /* The remaining Trusted SRAM is used to load the BL images */ 66 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 67 ARM_SHARED_RAM_SIZE) 68 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 69 ARM_SHARED_RAM_SIZE) 70 71 /* 72 * The top 16MB of DRAM1 is configured as secure access only using the TZC 73 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 74 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 75 */ 76 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) 77 78 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 79 ARM_DRAM1_SIZE - \ 80 ARM_SCP_TZC_DRAM1_SIZE) 81 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 82 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 83 ARM_SCP_TZC_DRAM1_SIZE - 1) 84 85 /* 86 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 87 * firmware. This region is meant to be NOLOAD and will not be zero 88 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 89 * placed here. 90 */ 91 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 92 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ 93 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 94 ARM_EL3_TZC_DRAM1_SIZE - 1) 95 96 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 97 ARM_DRAM1_SIZE - \ 98 ARM_TZC_DRAM1_SIZE) 99 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 100 (ARM_SCP_TZC_DRAM1_SIZE + \ 101 ARM_EL3_TZC_DRAM1_SIZE)) 102 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 103 ARM_AP_TZC_DRAM1_SIZE - 1) 104 105 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 106 #if ARM_CRYPTOCELL_INTEG 107 /* 108 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 109 * This is required by CryptoCell to authenticate BL33 which is loaded 110 * into the Non Secure DDR. 111 */ 112 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 113 #else 114 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 115 #endif 116 117 #ifdef SPD_opteed 118 /* 119 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 120 * load/authenticate the trusted os extra image. The first 512KB of 121 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 122 * for OPTEE is paged image which only include the paging part using 123 * virtual memory but without "init" data. OPTEE will copy the "init" data 124 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 125 * extra image behind the "init" data. 126 */ 127 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 128 ARM_AP_TZC_DRAM1_SIZE - \ 129 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 130 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 131 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 132 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 133 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 134 MT_MEMORY | MT_RW | MT_SECURE) 135 136 /* 137 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 138 * support is enabled). 139 */ 140 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 141 BL32_BASE, \ 142 BL32_LIMIT - BL32_BASE, \ 143 MT_MEMORY | MT_RW | MT_SECURE) 144 #endif /* SPD_opteed */ 145 146 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 147 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 148 ARM_TZC_DRAM1_SIZE) 149 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 150 ARM_NS_DRAM1_SIZE - 1) 151 152 #define ARM_DRAM1_BASE ULL(0x80000000) 153 #define ARM_DRAM1_SIZE ULL(0x80000000) 154 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 155 ARM_DRAM1_SIZE - 1) 156 157 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 158 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 159 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 160 ARM_DRAM2_SIZE - 1) 161 162 #define ARM_IRQ_SEC_PHY_TIMER 29 163 164 #define ARM_IRQ_SEC_SGI_0 8 165 #define ARM_IRQ_SEC_SGI_1 9 166 #define ARM_IRQ_SEC_SGI_2 10 167 #define ARM_IRQ_SEC_SGI_3 11 168 #define ARM_IRQ_SEC_SGI_4 12 169 #define ARM_IRQ_SEC_SGI_5 13 170 #define ARM_IRQ_SEC_SGI_6 14 171 #define ARM_IRQ_SEC_SGI_7 15 172 173 /* 174 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 175 * terminology. On a GICv2 system or mode, the lists will be merged and treated 176 * as Group 0 interrupts. 177 */ 178 #define ARM_G1S_IRQ_PROPS(grp) \ 179 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 180 GIC_INTR_CFG_LEVEL), \ 181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 182 GIC_INTR_CFG_EDGE), \ 183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 184 GIC_INTR_CFG_EDGE), \ 185 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 186 GIC_INTR_CFG_EDGE), \ 187 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 188 GIC_INTR_CFG_EDGE), \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 190 GIC_INTR_CFG_EDGE), \ 191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 192 GIC_INTR_CFG_EDGE) 193 194 #define ARM_G0_IRQ_PROPS(grp) \ 195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 196 GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 198 GIC_INTR_CFG_EDGE) 199 200 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 201 ARM_SHARED_RAM_BASE, \ 202 ARM_SHARED_RAM_SIZE, \ 203 MT_DEVICE | MT_RW | MT_SECURE) 204 205 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 206 ARM_NS_DRAM1_BASE, \ 207 ARM_NS_DRAM1_SIZE, \ 208 MT_MEMORY | MT_RW | MT_NS) 209 210 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 211 ARM_DRAM2_BASE, \ 212 ARM_DRAM2_SIZE, \ 213 MT_MEMORY | MT_RW | MT_NS) 214 215 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 216 TSP_SEC_MEM_BASE, \ 217 TSP_SEC_MEM_SIZE, \ 218 MT_MEMORY | MT_RW | MT_SECURE) 219 220 #if ARM_BL31_IN_DRAM 221 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 222 BL31_BASE, \ 223 PLAT_ARM_MAX_BL31_SIZE, \ 224 MT_MEMORY | MT_RW | MT_SECURE) 225 #endif 226 227 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 228 ARM_EL3_TZC_DRAM1_BASE, \ 229 ARM_EL3_TZC_DRAM1_SIZE, \ 230 MT_MEMORY | MT_RW | MT_SECURE) 231 232 #if defined(SPD_spmd) 233 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 234 PLAT_ARM_TRUSTED_DRAM_BASE, \ 235 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 236 MT_MEMORY | MT_RW | MT_SECURE) 237 #endif 238 239 240 /* 241 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 242 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 243 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 244 * to be able to access the heap. 245 */ 246 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 247 BL1_RW_BASE, \ 248 BL1_RW_LIMIT - BL1_RW_BASE, \ 249 MT_MEMORY | MT_RW | MT_SECURE) 250 251 /* 252 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 253 * otherwise one region is defined containing both. 254 */ 255 #if SEPARATE_CODE_AND_RODATA 256 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 257 BL_CODE_BASE, \ 258 BL_CODE_END - BL_CODE_BASE, \ 259 MT_CODE | MT_SECURE), \ 260 MAP_REGION_FLAT( \ 261 BL_RO_DATA_BASE, \ 262 BL_RO_DATA_END \ 263 - BL_RO_DATA_BASE, \ 264 MT_RO_DATA | MT_SECURE) 265 #else 266 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 267 BL_CODE_BASE, \ 268 BL_CODE_END - BL_CODE_BASE, \ 269 MT_CODE | MT_SECURE) 270 #endif 271 #if USE_COHERENT_MEM 272 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 273 BL_COHERENT_RAM_BASE, \ 274 BL_COHERENT_RAM_END \ 275 - BL_COHERENT_RAM_BASE, \ 276 MT_DEVICE | MT_RW | MT_SECURE) 277 #endif 278 #if USE_ROMLIB 279 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 280 ROMLIB_RO_BASE, \ 281 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 282 MT_CODE | MT_SECURE) 283 284 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 285 ROMLIB_RW_BASE, \ 286 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 287 MT_MEMORY | MT_RW | MT_SECURE) 288 #endif 289 290 /* 291 * Map mem_protect flash region with read and write permissions 292 */ 293 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 294 V2M_FLASH_BLOCK_SIZE, \ 295 MT_DEVICE | MT_RW | MT_SECURE) 296 297 /* 298 * The max number of regions like RO(code), coherent and data required by 299 * different BL stages which need to be mapped in the MMU. 300 */ 301 #define ARM_BL_REGIONS 5 302 303 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 304 ARM_BL_REGIONS) 305 306 /* Memory mapped Generic timer interfaces */ 307 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 308 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 309 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 310 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 311 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 312 313 #define ARM_CONSOLE_BAUDRATE 115200 314 315 /* Trusted Watchdog constants */ 316 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 317 #define ARM_SP805_TWDG_CLK_HZ 32768 318 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 319 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 320 #define ARM_TWDG_TIMEOUT_SEC 128 321 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 322 ARM_TWDG_TIMEOUT_SEC) 323 324 /****************************************************************************** 325 * Required platform porting definitions common to all ARM standard platforms 326 *****************************************************************************/ 327 328 /* 329 * This macro defines the deepest retention state possible. A higher state 330 * id will represent an invalid or a power down state. 331 */ 332 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 333 334 /* 335 * This macro defines the deepest power down states possible. Any state ID 336 * higher than this is invalid. 337 */ 338 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 339 340 /* 341 * Some data must be aligned on the biggest cache line size in the platform. 342 * This is known only to the platform as it might have a combination of 343 * integrated and external caches. 344 */ 345 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 346 347 /* 348 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 349 * and limit. Leave enough space of BL2 meminfo. 350 */ 351 #define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 352 #define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U)) 353 354 /* 355 * Boot parameters passed from BL2 to BL31/BL32 are stored here 356 */ 357 #define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT 358 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \ 359 (PAGE_SIZE / 2U)) 360 361 /* 362 * Define limit of firmware configuration memory: 363 * ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory 364 */ 365 #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) 366 367 /******************************************************************************* 368 * BL1 specific defines. 369 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 370 * addresses. 371 ******************************************************************************/ 372 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 373 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 374 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 375 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 376 /* 377 * Put BL1 RW at the top of the Trusted SRAM. 378 */ 379 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 380 ARM_BL_RAM_SIZE - \ 381 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 382 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 383 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 384 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 385 386 #define ROMLIB_RO_BASE BL1_RO_LIMIT 387 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 388 389 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 390 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 391 392 /******************************************************************************* 393 * BL2 specific defines. 394 ******************************************************************************/ 395 #if BL2_AT_EL3 396 /* Put BL2 towards the middle of the Trusted SRAM */ 397 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 398 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 399 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 400 401 #else 402 /* 403 * Put BL2 just below BL1. 404 */ 405 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 406 #define BL2_LIMIT BL1_RW_BASE 407 #endif 408 409 /******************************************************************************* 410 * BL31 specific defines. 411 ******************************************************************************/ 412 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 413 /* 414 * Put BL31 at the bottom of TZC secured DRAM 415 */ 416 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 417 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 418 PLAT_ARM_MAX_BL31_SIZE) 419 /* 420 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 421 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 422 */ 423 #if SEPARATE_NOBITS_REGION 424 #define BL31_NOBITS_BASE BL2_BASE 425 #define BL31_NOBITS_LIMIT BL2_LIMIT 426 #endif /* SEPARATE_NOBITS_REGION */ 427 #elif (RESET_TO_BL31) 428 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 429 # if !ENABLE_PIE 430 # error "BL31 must be a PIE if RESET_TO_BL31=1." 431 #endif 432 /* 433 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 434 * used for building BL31 and not used for loading BL31. 435 */ 436 # define BL31_BASE 0x0 437 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 438 #else 439 /* Put BL31 below BL2 in the Trusted SRAM.*/ 440 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 441 - PLAT_ARM_MAX_BL31_SIZE) 442 #define BL31_PROGBITS_LIMIT BL2_BASE 443 /* 444 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 445 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 446 */ 447 #if BL2_AT_EL3 448 #define BL31_LIMIT BL2_BASE 449 #else 450 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 451 #endif 452 #endif 453 454 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 455 /******************************************************************************* 456 * BL32 specific defines for EL3 runtime in AArch32 mode 457 ******************************************************************************/ 458 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 459 /* 460 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding 461 * the page reserved for fw_configs) to BL32 462 */ 463 # define BL32_BASE ARM_FW_CONFIG_LIMIT 464 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 465 # else 466 /* Put BL32 below BL2 in the Trusted SRAM.*/ 467 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 468 - PLAT_ARM_MAX_BL32_SIZE) 469 # define BL32_PROGBITS_LIMIT BL2_BASE 470 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 471 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 472 473 #else 474 /******************************************************************************* 475 * BL32 specific defines for EL3 runtime in AArch64 mode 476 ******************************************************************************/ 477 /* 478 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 479 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 480 * controller. 481 */ 482 # if SPM_MM 483 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 484 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 485 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 486 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 487 ARM_AP_TZC_DRAM1_SIZE) 488 # elif defined(SPD_spmd) 489 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 490 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 491 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 492 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 493 + (UL(1) << 21)) 494 # elif ARM_BL31_IN_DRAM 495 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 496 PLAT_ARM_MAX_BL31_SIZE) 497 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 498 PLAT_ARM_MAX_BL31_SIZE) 499 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 500 PLAT_ARM_MAX_BL31_SIZE) 501 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 502 ARM_AP_TZC_DRAM1_SIZE) 503 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 504 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 505 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 506 # define TSP_PROGBITS_LIMIT BL31_BASE 507 # define BL32_BASE ARM_FW_CONFIG_LIMIT 508 # define BL32_LIMIT BL31_BASE 509 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 510 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 511 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 512 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 513 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 514 + (UL(1) << 21)) 515 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 516 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 517 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 518 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 519 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 520 ARM_AP_TZC_DRAM1_SIZE) 521 # else 522 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 523 # endif 524 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 525 526 /* 527 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 528 * SPD and no SPM-MM, as they are the only ones that can be used as BL32. 529 */ 530 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 531 # if defined(SPD_none) && !SPM_MM 532 # undef BL32_BASE 533 # endif /* defined(SPD_none) && !SPM_MM */ 534 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 535 536 /******************************************************************************* 537 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 538 ******************************************************************************/ 539 #define BL2U_BASE BL2_BASE 540 #define BL2U_LIMIT BL2_LIMIT 541 542 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 543 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 544 545 /* 546 * ID of the secure physical generic timer interrupt used by the TSP. 547 */ 548 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 549 550 551 /* 552 * One cache line needed for bakery locks on ARM platforms 553 */ 554 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 555 556 /* Priority levels for ARM platforms */ 557 #define PLAT_RAS_PRI 0x10 558 #define PLAT_SDEI_CRITICAL_PRI 0x60 559 #define PLAT_SDEI_NORMAL_PRI 0x70 560 561 /* ARM platforms use 3 upper bits of secure interrupt priority */ 562 #define ARM_PRI_BITS 3 563 564 /* SGI used for SDEI signalling */ 565 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 566 567 /* ARM SDEI dynamic private event numbers */ 568 #define ARM_SDEI_DP_EVENT_0 1000 569 #define ARM_SDEI_DP_EVENT_1 1001 570 #define ARM_SDEI_DP_EVENT_2 1002 571 572 /* ARM SDEI dynamic shared event numbers */ 573 #define ARM_SDEI_DS_EVENT_0 2000 574 #define ARM_SDEI_DS_EVENT_1 2001 575 #define ARM_SDEI_DS_EVENT_2 2002 576 577 #define ARM_SDEI_PRIVATE_EVENTS \ 578 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 579 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 580 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 581 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 582 583 #define ARM_SDEI_SHARED_EVENTS \ 584 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 585 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 586 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 587 588 #endif /* ARM_DEF_H */ 589