1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common/interrupt_props.h> 11 #include <common/tbbr/tbbr_img_def.h> 12 #include <drivers/arm/gic_common.h> 13 #include <lib/utils_def.h> 14 #include <lib/xlat_tables/xlat_tables_defs.h> 15 #include <plat/arm/board/common/rotpk/rotpk_def.h> 16 #include <plat/arm/common/smccc_def.h> 17 #include <plat/common/common_def.h> 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 24 /* Special value used to verify platform parameters from BL2 to BL31 */ 25 #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) 26 27 #define ARM_SYSTEM_COUNT U(1) 28 29 #define ARM_CACHE_WRITEBACK_SHIFT 6 30 31 /* 32 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 33 * power levels have a 1:1 mapping with the MPIDR affinity levels. 34 */ 35 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 36 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 37 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 38 #define ARM_PWR_LVL3 MPIDR_AFFLVL3 39 40 /* 41 * Macros for local power states in ARM platforms encoded by State-ID field 42 * within the power-state parameter. 43 */ 44 /* Local power state for power domains in Run state. */ 45 #define ARM_LOCAL_STATE_RUN U(0) 46 /* Local power state for retention. Valid only for CPU power domains */ 47 #define ARM_LOCAL_STATE_RET U(1) 48 /* Local power state for OFF/power-down. Valid for CPU and cluster power 49 domains */ 50 #define ARM_LOCAL_STATE_OFF U(2) 51 52 /* Memory location options for TSP */ 53 #define ARM_TRUSTED_SRAM_ID 0 54 #define ARM_TRUSTED_DRAM_ID 1 55 #define ARM_DRAM_ID 2 56 57 #ifdef PLAT_ARM_TRUSTED_SRAM_BASE 58 #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE 59 #else 60 #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) 61 #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ 62 63 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 64 #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ 65 66 /* The remaining Trusted SRAM is used to load the BL images */ 67 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 68 ARM_SHARED_RAM_SIZE) 69 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 70 ARM_SHARED_RAM_SIZE) 71 72 /* 73 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as 74 * follows: 75 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 76 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled 77 * - REALM DRAM: Reserved for Realm world if RME is enabled 78 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM 79 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled 80 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 81 * 82 * RME enabled(64MB) RME not enabled(16MB) 83 * -------------------- ------------------- 84 * | | | | 85 * | AP TZC (~28MB) | | AP TZC (~14MB) | 86 * -------------------- ------------------- 87 * | Event Log | | Event Log | 88 * | (4KB) | | (4KB) | 89 * -------------------- ------------------- 90 * | REALM (RMM) | | | 91 * | (32MB - 4KB) | | EL3 TZC (2MB) | 92 * -------------------- ------------------- 93 * | | | | 94 * | TF-A <-> RMM | | SCP TZC | 95 * | SHARED (4KB) | 0xFFFF_FFFF------------------- 96 * -------------------- 97 * | | 98 * | EL3 TZC (3MB) | 99 * -------------------- 100 * | L1 GPT + SCP TZC | 101 * | (~1MB) | 102 * 0xFFFF_FFFF -------------------- 103 */ 104 #if ENABLE_RME 105 #define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */ 106 /* 107 * Define a region within the TZC secured DRAM for use by EL3 runtime 108 * firmware. This region is meant to be NOLOAD and will not be zero 109 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be 110 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise. 111 */ 112 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */ 113 #define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */ 114 /* 32MB - ARM_EL3_RMM_SHARED_SIZE */ 115 #define ARM_REALM_SIZE (UL(0x02000000) - \ 116 ARM_EL3_RMM_SHARED_SIZE) 117 #define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */ 118 #else 119 #define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */ 120 #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */ 121 #define ARM_L1_GPT_SIZE UL(0) 122 #define ARM_REALM_SIZE UL(0) 123 #define ARM_EL3_RMM_SHARED_SIZE UL(0) 124 #endif /* ENABLE_RME */ 125 126 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 127 ARM_DRAM1_SIZE - \ 128 (ARM_SCP_TZC_DRAM1_SIZE + \ 129 ARM_L1_GPT_SIZE)) 130 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 131 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 132 ARM_SCP_TZC_DRAM1_SIZE - 1U) 133 134 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 135 MEASURED_BOOT 136 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */ 137 138 #if ENABLE_RME 139 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \ 140 ARM_EVENT_LOG_DRAM1_SIZE) 141 #else 142 #define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \ 143 ARM_EVENT_LOG_DRAM1_SIZE) 144 #endif /* ENABLE_RME */ 145 #define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \ 146 ARM_EVENT_LOG_DRAM1_SIZE - \ 147 1U) 148 #else 149 #define ARM_EVENT_LOG_DRAM1_SIZE UL(0) 150 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 151 152 #if ENABLE_RME 153 #define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \ 154 ARM_DRAM1_SIZE - \ 155 ARM_L1_GPT_SIZE) 156 #define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \ 157 ARM_L1_GPT_SIZE - 1U) 158 159 #define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \ 160 ARM_REALM_SIZE) 161 162 #define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U) 163 164 #define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \ 165 ARM_DRAM1_SIZE - \ 166 (ARM_SCP_TZC_DRAM1_SIZE + \ 167 ARM_L1_GPT_SIZE + \ 168 ARM_EL3_RMM_SHARED_SIZE + \ 169 ARM_EL3_TZC_DRAM1_SIZE)) 170 171 #define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \ 172 ARM_EL3_RMM_SHARED_SIZE - 1U) 173 #endif /* ENABLE_RME */ 174 175 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \ 176 ARM_EL3_TZC_DRAM1_SIZE) 177 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 178 ARM_EL3_TZC_DRAM1_SIZE - 1U) 179 180 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 181 ARM_DRAM1_SIZE - \ 182 ARM_TZC_DRAM1_SIZE) 183 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 184 (ARM_SCP_TZC_DRAM1_SIZE + \ 185 ARM_EL3_TZC_DRAM1_SIZE + \ 186 ARM_EL3_RMM_SHARED_SIZE + \ 187 ARM_REALM_SIZE + \ 188 ARM_L1_GPT_SIZE + \ 189 ARM_EVENT_LOG_DRAM1_SIZE)) 190 191 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 192 ARM_AP_TZC_DRAM1_SIZE - 1U) 193 194 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 195 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 196 197 #ifdef SPD_opteed 198 /* 199 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 200 * load/authenticate the trusted os extra image. The first 512KB of 201 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 202 * for OPTEE is paged image which only include the paging part using 203 * virtual memory but without "init" data. OPTEE will copy the "init" data 204 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 205 * extra image behind the "init" data. 206 */ 207 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 208 ARM_AP_TZC_DRAM1_SIZE - \ 209 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 210 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) 211 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 212 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 213 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 214 MT_MEMORY | MT_RW | MT_SECURE) 215 216 /* 217 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 218 * support is enabled). 219 */ 220 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 221 BL32_BASE, \ 222 BL32_LIMIT - BL32_BASE, \ 223 MT_MEMORY | MT_RW | MT_SECURE) 224 #endif /* SPD_opteed */ 225 226 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 227 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 228 ARM_TZC_DRAM1_SIZE) 229 230 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 231 ARM_NS_DRAM1_SIZE - 1U) 232 #ifdef PLAT_ARM_DRAM1_BASE 233 #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE 234 #else 235 #define ARM_DRAM1_BASE ULL(0x80000000) 236 #endif /* PLAT_ARM_DRAM1_BASE */ 237 238 #define ARM_DRAM1_SIZE ULL(0x80000000) 239 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 240 ARM_DRAM1_SIZE - 1U) 241 242 #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE 243 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 244 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 245 ARM_DRAM2_SIZE - 1U) 246 /* Number of DRAM banks */ 247 #define ARM_DRAM_NUM_BANKS 2UL 248 249 #define ARM_IRQ_SEC_PHY_TIMER 29 250 251 #define ARM_IRQ_SEC_SGI_0 8 252 #define ARM_IRQ_SEC_SGI_1 9 253 #define ARM_IRQ_SEC_SGI_2 10 254 #define ARM_IRQ_SEC_SGI_3 11 255 #define ARM_IRQ_SEC_SGI_4 12 256 #define ARM_IRQ_SEC_SGI_5 13 257 #define ARM_IRQ_SEC_SGI_6 14 258 #define ARM_IRQ_SEC_SGI_7 15 259 260 /* 261 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 262 * terminology. On a GICv2 system or mode, the lists will be merged and treated 263 * as Group 0 interrupts. 264 */ 265 #define ARM_G1S_IRQ_PROPS(grp) \ 266 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 267 GIC_INTR_CFG_LEVEL), \ 268 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 269 GIC_INTR_CFG_EDGE), \ 270 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 271 GIC_INTR_CFG_EDGE), \ 272 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 273 GIC_INTR_CFG_EDGE), \ 274 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 275 GIC_INTR_CFG_EDGE), \ 276 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 277 GIC_INTR_CFG_EDGE), \ 278 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 279 GIC_INTR_CFG_EDGE) 280 281 #define ARM_G0_IRQ_PROPS(grp) \ 282 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ 283 GIC_INTR_CFG_EDGE), \ 284 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ 285 GIC_INTR_CFG_EDGE) 286 287 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 288 ARM_SHARED_RAM_BASE, \ 289 ARM_SHARED_RAM_SIZE, \ 290 MT_DEVICE | MT_RW | EL3_PAS) 291 292 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 293 ARM_NS_DRAM1_BASE, \ 294 ARM_NS_DRAM1_SIZE, \ 295 MT_MEMORY | MT_RW | MT_NS) 296 297 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 298 ARM_DRAM2_BASE, \ 299 ARM_DRAM2_SIZE, \ 300 MT_MEMORY | MT_RW | MT_NS) 301 302 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 303 TSP_SEC_MEM_BASE, \ 304 TSP_SEC_MEM_SIZE, \ 305 MT_MEMORY | MT_RW | MT_SECURE) 306 307 #if ARM_BL31_IN_DRAM 308 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 309 BL31_BASE, \ 310 PLAT_ARM_MAX_BL31_SIZE, \ 311 MT_MEMORY | MT_RW | MT_SECURE) 312 #endif 313 314 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 315 ARM_EL3_TZC_DRAM1_BASE, \ 316 ARM_EL3_TZC_DRAM1_SIZE, \ 317 MT_MEMORY | MT_RW | EL3_PAS) 318 319 #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ 320 PLAT_ARM_TRUSTED_DRAM_BASE, \ 321 PLAT_ARM_TRUSTED_DRAM_SIZE, \ 322 MT_MEMORY | MT_RW | MT_SECURE) 323 324 # if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \ 325 MEASURED_BOOT 326 #define ARM_MAP_EVENT_LOG_DRAM1 \ 327 MAP_REGION_FLAT( \ 328 ARM_EVENT_LOG_DRAM1_BASE, \ 329 ARM_EVENT_LOG_DRAM1_SIZE, \ 330 MT_MEMORY | MT_RW | MT_SECURE) 331 #endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */ 332 333 #if ENABLE_RME 334 /* 335 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block. 336 * Else we end up requiring more pagetables in BL2 for ROMLIB build. 337 */ 338 #define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \ 339 PLAT_ARM_RMM_BASE, \ 340 (PLAT_ARM_RMM_SIZE + \ 341 ARM_EL3_RMM_SHARED_SIZE), \ 342 MT_MEMORY | MT_RW | MT_REALM) 343 344 345 #define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \ 346 ARM_L1_GPT_BASE, \ 347 ARM_L1_GPT_SIZE, \ 348 MT_MEMORY | MT_RW | EL3_PAS) 349 350 #define ARM_MAP_EL3_RMM_SHARED_MEM \ 351 MAP_REGION_FLAT( \ 352 ARM_EL3_RMM_SHARED_BASE, \ 353 ARM_EL3_RMM_SHARED_SIZE, \ 354 MT_MEMORY | MT_RW | MT_REALM) 355 356 #endif /* ENABLE_RME */ 357 358 /* 359 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to 360 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides 361 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order 362 * to be able to access the heap. 363 */ 364 #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ 365 BL1_RW_BASE, \ 366 BL1_RW_LIMIT - BL1_RW_BASE, \ 367 MT_MEMORY | MT_RW | EL3_PAS) 368 369 /* 370 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 371 * otherwise one region is defined containing both. 372 */ 373 #if SEPARATE_CODE_AND_RODATA 374 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 375 BL_CODE_BASE, \ 376 BL_CODE_END - BL_CODE_BASE, \ 377 MT_CODE | EL3_PAS), \ 378 MAP_REGION_FLAT( \ 379 BL_RO_DATA_BASE, \ 380 BL_RO_DATA_END \ 381 - BL_RO_DATA_BASE, \ 382 MT_RO_DATA | EL3_PAS) 383 #else 384 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 385 BL_CODE_BASE, \ 386 BL_CODE_END - BL_CODE_BASE, \ 387 MT_CODE | EL3_PAS) 388 #endif 389 #if USE_COHERENT_MEM 390 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 391 BL_COHERENT_RAM_BASE, \ 392 BL_COHERENT_RAM_END \ 393 - BL_COHERENT_RAM_BASE, \ 394 MT_DEVICE | MT_RW | EL3_PAS) 395 #endif 396 #if USE_ROMLIB 397 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 398 ROMLIB_RO_BASE, \ 399 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 400 MT_CODE | EL3_PAS) 401 402 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 403 ROMLIB_RW_BASE, \ 404 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 405 MT_MEMORY | MT_RW | EL3_PAS) 406 #endif 407 408 /* 409 * Map mem_protect flash region with read and write permissions 410 */ 411 #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ 412 V2M_FLASH_BLOCK_SIZE, \ 413 MT_DEVICE | MT_RW | MT_SECURE) 414 /* 415 * Map the region for device tree configuration with read and write permissions 416 */ 417 #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ 418 (ARM_FW_CONFIGS_LIMIT \ 419 - ARM_BL_RAM_BASE), \ 420 MT_MEMORY | MT_RW | EL3_PAS) 421 /* 422 * Map L0_GPT with read and write permissions 423 */ 424 #if ENABLE_RME 425 #define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \ 426 ARM_L0_GPT_SIZE, \ 427 MT_MEMORY | MT_RW | MT_ROOT) 428 #endif 429 430 /* 431 * The max number of regions like RO(code), coherent and data required by 432 * different BL stages which need to be mapped in the MMU. 433 */ 434 #define ARM_BL_REGIONS 7 435 436 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 437 ARM_BL_REGIONS) 438 439 /* Memory mapped Generic timer interfaces */ 440 #ifdef PLAT_ARM_SYS_CNTCTL_BASE 441 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE 442 #else 443 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) 444 #endif 445 446 #ifdef PLAT_ARM_SYS_CNTREAD_BASE 447 #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE 448 #else 449 #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) 450 #endif 451 452 #ifdef PLAT_ARM_SYS_TIMCTL_BASE 453 #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE 454 #else 455 #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) 456 #endif 457 458 #ifdef PLAT_ARM_SYS_CNT_BASE_S 459 #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S 460 #else 461 #define ARM_SYS_CNT_BASE_S UL(0x2a820000) 462 #endif 463 464 #ifdef PLAT_ARM_SYS_CNT_BASE_NS 465 #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS 466 #else 467 #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) 468 #endif 469 470 #define ARM_CONSOLE_BAUDRATE 115200 471 472 /* Trusted Watchdog constants */ 473 #ifdef PLAT_ARM_SP805_TWDG_BASE 474 #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE 475 #else 476 #define ARM_SP805_TWDG_BASE UL(0x2a490000) 477 #endif 478 #define ARM_SP805_TWDG_CLK_HZ 32768 479 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 480 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 481 #define ARM_TWDG_TIMEOUT_SEC 128 482 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 483 ARM_TWDG_TIMEOUT_SEC) 484 485 /****************************************************************************** 486 * Required platform porting definitions common to all ARM standard platforms 487 *****************************************************************************/ 488 489 /* 490 * This macro defines the deepest retention state possible. A higher state 491 * id will represent an invalid or a power down state. 492 */ 493 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 494 495 /* 496 * This macro defines the deepest power down states possible. Any state ID 497 * higher than this is invalid. 498 */ 499 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 500 501 /* 502 * Some data must be aligned on the biggest cache line size in the platform. 503 * This is known only to the platform as it might have a combination of 504 * integrated and external caches. 505 */ 506 #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) 507 508 /* 509 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base 510 * and limit. Leave enough space of BL2 meminfo. 511 */ 512 #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) 513 #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ 514 + (PAGE_SIZE / 2U)) 515 516 /* 517 * Boot parameters passed from BL2 to BL31/BL32 are stored here 518 */ 519 #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) 520 #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ 521 + (PAGE_SIZE / 2U)) 522 523 /* 524 * Define limit of firmware configuration memory: 525 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory 526 */ 527 #define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2) 528 #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE) 529 530 #if ENABLE_RME 531 /* 532 * Store the L0 GPT on Trusted SRAM next to firmware 533 * configuration memory, 4KB aligned. 534 */ 535 #define ARM_L0_GPT_SIZE (PAGE_SIZE) 536 #define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT) 537 #define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE) 538 #else 539 #define ARM_L0_GPT_SIZE U(0) 540 #endif 541 542 /******************************************************************************* 543 * BL1 specific defines. 544 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 545 * addresses. 546 ******************************************************************************/ 547 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 548 #ifdef PLAT_BL1_RO_LIMIT 549 #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT 550 #else 551 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 552 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 553 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 554 #endif 555 556 /* 557 * Put BL1 RW at the top of the Trusted SRAM. 558 */ 559 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 560 ARM_BL_RAM_SIZE - \ 561 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 562 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 563 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 564 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 565 566 #define ROMLIB_RO_BASE BL1_RO_LIMIT 567 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 568 569 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 570 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 571 572 /******************************************************************************* 573 * BL2 specific defines. 574 ******************************************************************************/ 575 #if RESET_TO_BL2 576 #if ENABLE_PIE 577 /* 578 * As the BL31 image size appears to be increased when built with the ENABLE_PIE 579 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM. 580 */ 581 #define BL2_OFFSET (0x5000) 582 #else 583 /* Put BL2 towards the middle of the Trusted SRAM */ 584 #define BL2_OFFSET (0x2000) 585 #endif /* ENABLE_PIE */ 586 587 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 588 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \ 589 BL2_OFFSET) 590 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 591 592 #else 593 /* 594 * Put BL2 just below BL1. 595 */ 596 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 597 #define BL2_LIMIT BL1_RW_BASE 598 #endif 599 600 /******************************************************************************* 601 * BL31 specific defines. 602 ******************************************************************************/ 603 #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION 604 /* 605 * Put BL31 at the bottom of TZC secured DRAM 606 */ 607 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 608 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 609 PLAT_ARM_MAX_BL31_SIZE) 610 /* 611 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. 612 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. 613 */ 614 #if SEPARATE_NOBITS_REGION 615 #define BL31_NOBITS_BASE BL2_BASE 616 #define BL31_NOBITS_LIMIT BL2_LIMIT 617 #endif /* SEPARATE_NOBITS_REGION */ 618 #elif (RESET_TO_BL31) 619 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 620 # if !ENABLE_PIE 621 # error "BL31 must be a PIE if RESET_TO_BL31=1." 622 #endif 623 /* 624 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely 625 * used for building BL31 and not used for loading BL31. 626 */ 627 # define BL31_BASE 0x0 628 # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE 629 #else 630 /* Put BL31 below BL2 in the Trusted SRAM.*/ 631 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 632 - PLAT_ARM_MAX_BL31_SIZE) 633 #define BL31_PROGBITS_LIMIT BL2_BASE 634 /* 635 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE. 636 * This is because in the RESET_TO_BL2 configuration, 637 * BL2 is always resident. 638 */ 639 #if RESET_TO_BL2 640 #define BL31_LIMIT BL2_BASE 641 #else 642 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 643 #endif 644 #endif 645 646 /****************************************************************************** 647 * RMM specific defines 648 *****************************************************************************/ 649 #if ENABLE_RME 650 #define RMM_BASE (ARM_REALM_BASE) 651 #define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE) 652 #define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE) 653 #define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE) 654 #endif 655 656 #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME 657 /******************************************************************************* 658 * BL32 specific defines for EL3 runtime in AArch32 mode 659 ******************************************************************************/ 660 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 661 /* Ensure Position Independent support (PIE) is enabled for this config.*/ 662 # if !ENABLE_PIE 663 # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." 664 #endif 665 /* 666 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely 667 * used for building BL32 and not used for loading BL32. 668 */ 669 # define BL32_BASE 0x0 670 # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE 671 # else 672 /* Put BL32 below BL2 in the Trusted SRAM.*/ 673 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 674 - PLAT_ARM_MAX_BL32_SIZE) 675 # define BL32_PROGBITS_LIMIT BL2_BASE 676 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 677 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 678 679 #else 680 /******************************************************************************* 681 * BL32 specific defines for EL3 runtime in AArch64 mode 682 ******************************************************************************/ 683 /* 684 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 685 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 686 * controller. 687 */ 688 # if SPM_MM || SPMC_AT_EL3 689 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 690 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 691 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 692 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 693 ARM_AP_TZC_DRAM1_SIZE) 694 # elif defined(SPD_spmd) 695 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 696 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 697 # define BL32_BASE PLAT_ARM_SPMC_BASE 698 # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ 699 PLAT_ARM_SPMC_SIZE) 700 # elif ARM_BL31_IN_DRAM 701 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 702 PLAT_ARM_MAX_BL31_SIZE) 703 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 704 PLAT_ARM_MAX_BL31_SIZE) 705 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 706 PLAT_ARM_MAX_BL31_SIZE) 707 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 708 ARM_AP_TZC_DRAM1_SIZE) 709 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 710 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 711 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 712 # define TSP_PROGBITS_LIMIT BL31_BASE 713 # define BL32_BASE ARM_FW_CONFIGS_LIMIT 714 # define BL32_LIMIT BL31_BASE 715 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 716 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 717 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 718 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 719 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 720 + SZ_4M) 721 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 722 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 723 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 724 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 725 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 726 ARM_AP_TZC_DRAM1_SIZE) 727 # else 728 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 729 # endif 730 #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ 731 732 /* 733 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 734 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be 735 * used as BL32. 736 */ 737 #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME 738 # if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3 739 # undef BL32_BASE 740 # endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */ 741 #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ 742 743 /******************************************************************************* 744 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 745 ******************************************************************************/ 746 #define BL2U_BASE BL2_BASE 747 #define BL2U_LIMIT BL2_LIMIT 748 749 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 750 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) 751 752 /* 753 * ID of the secure physical generic timer interrupt used by the TSP. 754 */ 755 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 756 757 758 /* 759 * One cache line needed for bakery locks on ARM platforms 760 */ 761 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 762 763 /* Priority levels for ARM platforms */ 764 #if ENABLE_FEAT_RAS && FFH_SUPPORT 765 #define PLAT_RAS_PRI 0x10 766 #endif 767 #define PLAT_SDEI_CRITICAL_PRI 0x60 768 #define PLAT_SDEI_NORMAL_PRI 0x70 769 770 /* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */ 771 #define PLAT_CORE_FAULT_IRQ 17 772 773 /* ARM platforms use 3 upper bits of secure interrupt priority */ 774 #define PLAT_PRI_BITS 3 775 776 /* SGI used for SDEI signalling */ 777 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 778 779 #if SDEI_IN_FCONF 780 /* ARM SDEI dynamic private event max count */ 781 #define ARM_SDEI_DP_EVENT_MAX_CNT 3 782 783 /* ARM SDEI dynamic shared event max count */ 784 #define ARM_SDEI_DS_EVENT_MAX_CNT 3 785 #else 786 /* ARM SDEI dynamic private event numbers */ 787 #define ARM_SDEI_DP_EVENT_0 1000 788 #define ARM_SDEI_DP_EVENT_1 1001 789 #define ARM_SDEI_DP_EVENT_2 1002 790 791 /* ARM SDEI dynamic shared event numbers */ 792 #define ARM_SDEI_DS_EVENT_0 2000 793 #define ARM_SDEI_DS_EVENT_1 2001 794 #define ARM_SDEI_DS_EVENT_2 2002 795 796 #define ARM_SDEI_PRIVATE_EVENTS \ 797 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 798 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 799 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 800 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 801 802 #define ARM_SDEI_SHARED_EVENTS \ 803 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 804 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 805 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 806 #endif /* SDEI_IN_FCONF */ 807 808 #endif /* ARM_DEF_H */ 809