1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 #ifndef __ARM_DEF_H__ 31 #define __ARM_DEF_H__ 32 33 #include <common_def.h> 34 #include <platform_def.h> 35 #include <tbbr_img_def.h> 36 #include <xlat_tables.h> 37 38 39 /****************************************************************************** 40 * Definitions common to all ARM standard platforms 41 *****************************************************************************/ 42 43 /* Special value used to verify platform parameters from BL2 to BL3-1 */ 44 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 45 46 #define ARM_CLUSTER_COUNT 2ull 47 48 #define ARM_CACHE_WRITEBACK_SHIFT 6 49 50 /* Memory location options for TSP */ 51 #define ARM_TRUSTED_SRAM_ID 0 52 #define ARM_TRUSTED_DRAM_ID 1 53 #define ARM_DRAM_ID 2 54 55 /* The first 4KB of Trusted SRAM are used as shared memory */ 56 #define ARM_TRUSTED_SRAM_BASE 0x04000000 57 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 58 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 59 60 /* The remaining Trusted SRAM is used to load the BL images */ 61 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 62 ARM_SHARED_RAM_SIZE) 63 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 64 ARM_SHARED_RAM_SIZE) 65 66 /* 67 * The top 16MB of DRAM1 is configured as secure access only using the TZC 68 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 69 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 70 */ 71 #define ARM_TZC_DRAM1_SIZE MAKE_ULL(0x01000000) 72 73 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 74 ARM_DRAM1_SIZE - \ 75 ARM_SCP_TZC_DRAM1_SIZE) 76 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 77 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 78 ARM_SCP_TZC_DRAM1_SIZE - 1) 79 80 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 81 ARM_DRAM1_SIZE - \ 82 ARM_TZC_DRAM1_SIZE) 83 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 84 ARM_SCP_TZC_DRAM1_SIZE) 85 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 86 ARM_AP_TZC_DRAM1_SIZE - 1) 87 88 89 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 90 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 91 ARM_TZC_DRAM1_SIZE) 92 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 93 ARM_NS_DRAM1_SIZE - 1) 94 95 #define ARM_DRAM1_BASE MAKE_ULL(0x80000000) 96 #define ARM_DRAM1_SIZE MAKE_ULL(0x80000000) 97 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 98 ARM_DRAM1_SIZE - 1) 99 100 #define ARM_DRAM2_BASE MAKE_ULL(0x880000000) 101 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 102 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 103 ARM_DRAM2_SIZE - 1) 104 105 #define ARM_IRQ_SEC_PHY_TIMER 29 106 107 #define ARM_IRQ_SEC_SGI_0 8 108 #define ARM_IRQ_SEC_SGI_1 9 109 #define ARM_IRQ_SEC_SGI_2 10 110 #define ARM_IRQ_SEC_SGI_3 11 111 #define ARM_IRQ_SEC_SGI_4 12 112 #define ARM_IRQ_SEC_SGI_5 13 113 #define ARM_IRQ_SEC_SGI_6 14 114 #define ARM_IRQ_SEC_SGI_7 15 115 116 #define ARM_SHARED_RAM_ATTR ((PLAT_ARM_SHARED_RAM_CACHED ? \ 117 MT_MEMORY : MT_DEVICE) \ 118 | MT_RW | MT_SECURE) 119 120 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 121 ARM_SHARED_RAM_BASE, \ 122 ARM_SHARED_RAM_SIZE, \ 123 ARM_SHARED_RAM_ATTR) 124 125 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 126 ARM_NS_DRAM1_BASE, \ 127 ARM_NS_DRAM1_SIZE, \ 128 MT_MEMORY | MT_RW | MT_NS) 129 130 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 131 TSP_SEC_MEM_BASE, \ 132 TSP_SEC_MEM_SIZE, \ 133 MT_MEMORY | MT_RW | MT_SECURE) 134 135 136 /* 137 * The number of regions like RO(code), coherent and data required by 138 * different BL stages which need to be mapped in the MMU. 139 */ 140 #if USE_COHERENT_MEM 141 #define ARM_BL_REGIONS 3 142 #else 143 #define ARM_BL_REGIONS 2 144 #endif 145 146 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 147 ARM_BL_REGIONS) 148 149 /* Memory mapped Generic timer interfaces */ 150 #define ARM_SYS_CNTCTL_BASE 0x2a430000 151 #define ARM_SYS_CNTREAD_BASE 0x2a800000 152 #define ARM_SYS_TIMCTL_BASE 0x2a810000 153 154 #define ARM_CONSOLE_BAUDRATE 115200 155 156 /* TZC related constants */ 157 #define ARM_TZC_BASE 0x2a4a0000 158 159 160 /****************************************************************************** 161 * Required platform porting definitions common to all ARM standard platforms 162 *****************************************************************************/ 163 164 #define ADDR_SPACE_SIZE (1ull << 32) 165 166 #define PLATFORM_NUM_AFFS (ARM_CLUSTER_COUNT + \ 167 PLATFORM_CORE_COUNT) 168 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1 169 170 #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER0_CORE_COUNT + \ 171 PLAT_ARM_CLUSTER1_CORE_COUNT) 172 173 /* 174 * Some data must be aligned on the biggest cache line size in the platform. 175 * This is known only to the platform as it might have a combination of 176 * integrated and external caches. 177 */ 178 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 179 180 #if !USE_COHERENT_MEM 181 /* 182 * Size of the per-cpu data in bytes that should be reserved in the generic 183 * per-cpu data structure for the ARM platform port. 184 */ 185 #define PLAT_PCPU_DATA_SIZE 2 186 #endif 187 188 189 /******************************************************************************* 190 * BL1 specific defines. 191 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 192 * addresses. 193 ******************************************************************************/ 194 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 195 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 196 + PLAT_ARM_TRUSTED_ROM_SIZE) 197 /* 198 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 199 * the current BL1 RW debug size plus a little space for growth. 200 */ 201 #if TRUSTED_BOARD_BOOT 202 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 203 ARM_BL_RAM_SIZE - \ 204 0x9000) 205 #else 206 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 207 ARM_BL_RAM_SIZE - \ 208 0x6000) 209 #endif 210 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 211 212 /******************************************************************************* 213 * BL2 specific defines. 214 ******************************************************************************/ 215 /* 216 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 217 * size plus a little space for growth. 218 */ 219 #if TRUSTED_BOARD_BOOT 220 #define BL2_BASE (BL31_BASE - 0x1D000) 221 #else 222 #define BL2_BASE (BL31_BASE - 0xC000) 223 #endif 224 #define BL2_LIMIT BL31_BASE 225 226 /******************************************************************************* 227 * BL3-1 specific defines. 228 ******************************************************************************/ 229 /* 230 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 231 * current BL3-1 debug size plus a little space for growth. 232 */ 233 #define BL31_BASE (ARM_BL_RAM_BASE + \ 234 ARM_BL_RAM_SIZE - \ 235 0x1D000) 236 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 237 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 238 239 /******************************************************************************* 240 * BL3-2 specific defines. 241 ******************************************************************************/ 242 /* 243 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 244 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 245 * controller. 246 */ 247 #if ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 248 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 249 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 250 # define TSP_PROGBITS_LIMIT BL2_BASE 251 # define BL32_BASE ARM_BL_RAM_BASE 252 # define BL32_LIMIT BL31_BASE 253 #elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 254 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 255 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 256 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 257 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 258 + (1 << 21)) 259 #elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 260 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 261 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 262 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 263 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 264 ARM_AP_TZC_DRAM1_SIZE) 265 #else 266 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 267 #endif 268 269 /* 270 * ID of the secure physical generic timer interrupt used by the TSP. 271 */ 272 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 273 274 275 #endif /* __ARM_DEF_H__ */ 276