1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef ARM_DEF_H 7 #define ARM_DEF_H 8 9 #include <arch.h> 10 #include <common_def.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <platform_def.h> 14 #include <tbbr_img_def.h> 15 #include <utils_def.h> 16 #include <xlat_tables_defs.h> 17 18 19 /****************************************************************************** 20 * Definitions common to all ARM standard platforms 21 *****************************************************************************/ 22 23 /* Special value used to verify platform parameters from BL2 to BL31 */ 24 #define ARM_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL 25 26 #define ARM_SYSTEM_COUNT 1 27 28 #define ARM_CACHE_WRITEBACK_SHIFT 6 29 30 /* 31 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The 32 * power levels have a 1:1 mapping with the MPIDR affinity levels. 33 */ 34 #define ARM_PWR_LVL0 MPIDR_AFFLVL0 35 #define ARM_PWR_LVL1 MPIDR_AFFLVL1 36 #define ARM_PWR_LVL2 MPIDR_AFFLVL2 37 38 /* 39 * Macros for local power states in ARM platforms encoded by State-ID field 40 * within the power-state parameter. 41 */ 42 /* Local power state for power domains in Run state. */ 43 #define ARM_LOCAL_STATE_RUN U(0) 44 /* Local power state for retention. Valid only for CPU power domains */ 45 #define ARM_LOCAL_STATE_RET U(1) 46 /* Local power state for OFF/power-down. Valid for CPU and cluster power 47 domains */ 48 #define ARM_LOCAL_STATE_OFF U(2) 49 50 /* Memory location options for TSP */ 51 #define ARM_TRUSTED_SRAM_ID 0 52 #define ARM_TRUSTED_DRAM_ID 1 53 #define ARM_DRAM_ID 2 54 55 /* The first 4KB of Trusted SRAM are used as shared memory */ 56 #define ARM_TRUSTED_SRAM_BASE 0x04000000 57 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE 58 #define ARM_SHARED_RAM_SIZE 0x00001000 /* 4 KB */ 59 60 /* The remaining Trusted SRAM is used to load the BL images */ 61 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ 62 ARM_SHARED_RAM_SIZE) 63 #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ 64 ARM_SHARED_RAM_SIZE) 65 66 /* 67 * The top 16MB of DRAM1 is configured as secure access only using the TZC 68 * - SCP TZC DRAM: If present, DRAM reserved for SCP use 69 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use 70 */ 71 #define ARM_TZC_DRAM1_SIZE ULL(0x01000000) 72 73 #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 74 ARM_DRAM1_SIZE - \ 75 ARM_SCP_TZC_DRAM1_SIZE) 76 #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE 77 #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ 78 ARM_SCP_TZC_DRAM1_SIZE - 1) 79 80 /* 81 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime 82 * firmware. This region is meant to be NOLOAD and will not be zero 83 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be 84 * placed here. 85 */ 86 #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) 87 #define ARM_EL3_TZC_DRAM1_SIZE ULL(0x00200000) /* 2 MB */ 88 #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ 89 ARM_EL3_TZC_DRAM1_SIZE - 1) 90 91 #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ 92 ARM_DRAM1_SIZE - \ 93 ARM_TZC_DRAM1_SIZE) 94 #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ 95 (ARM_SCP_TZC_DRAM1_SIZE + \ 96 ARM_EL3_TZC_DRAM1_SIZE)) 97 #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ 98 ARM_AP_TZC_DRAM1_SIZE - 1) 99 100 /* Define the Access permissions for Secure peripherals to NS_DRAM */ 101 #if ARM_CRYPTOCELL_INTEG 102 /* 103 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. 104 * This is required by CryptoCell to authenticate BL33 which is loaded 105 * into the Non Secure DDR. 106 */ 107 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD 108 #else 109 #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE 110 #endif 111 112 #ifdef SPD_opteed 113 /* 114 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to 115 * load/authenticate the trusted os extra image. The first 512KB of 116 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading 117 * for OPTEE is paged image which only include the paging part using 118 * virtual memory but without "init" data. OPTEE will copy the "init" data 119 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the 120 * extra image behind the "init" data. 121 */ 122 #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ 123 ARM_AP_TZC_DRAM1_SIZE - \ 124 ARM_OPTEE_PAGEABLE_LOAD_SIZE) 125 #define ARM_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 126 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ 127 ARM_OPTEE_PAGEABLE_LOAD_BASE, \ 128 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ 129 MT_MEMORY | MT_RW | MT_SECURE) 130 131 /* 132 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging 133 * support is enabled). 134 */ 135 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ 136 BL32_BASE, \ 137 BL32_LIMIT - BL32_BASE, \ 138 MT_MEMORY | MT_RW | MT_SECURE) 139 #endif /* SPD_opteed */ 140 141 #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE 142 #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 143 ARM_TZC_DRAM1_SIZE) 144 #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ 145 ARM_NS_DRAM1_SIZE - 1) 146 147 #define ARM_DRAM1_BASE ULL(0x80000000) 148 #define ARM_DRAM1_SIZE ULL(0x80000000) 149 #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ 150 ARM_DRAM1_SIZE - 1) 151 152 #define ARM_DRAM2_BASE ULL(0x880000000) 153 #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 154 #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ 155 ARM_DRAM2_SIZE - 1) 156 157 #define ARM_IRQ_SEC_PHY_TIMER 29 158 159 #define ARM_IRQ_SEC_SGI_0 8 160 #define ARM_IRQ_SEC_SGI_1 9 161 #define ARM_IRQ_SEC_SGI_2 10 162 #define ARM_IRQ_SEC_SGI_3 11 163 #define ARM_IRQ_SEC_SGI_4 12 164 #define ARM_IRQ_SEC_SGI_5 13 165 #define ARM_IRQ_SEC_SGI_6 14 166 #define ARM_IRQ_SEC_SGI_7 15 167 168 /* 169 * List of secure interrupts are deprecated, but are retained only to support 170 * legacy configurations. 171 */ 172 #define ARM_G1S_IRQS ARM_IRQ_SEC_PHY_TIMER, \ 173 ARM_IRQ_SEC_SGI_1, \ 174 ARM_IRQ_SEC_SGI_2, \ 175 ARM_IRQ_SEC_SGI_3, \ 176 ARM_IRQ_SEC_SGI_4, \ 177 ARM_IRQ_SEC_SGI_5, \ 178 ARM_IRQ_SEC_SGI_7 179 180 #define ARM_G0_IRQS ARM_IRQ_SEC_SGI_0, \ 181 ARM_IRQ_SEC_SGI_6 182 183 /* 184 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 185 * terminology. On a GICv2 system or mode, the lists will be merged and treated 186 * as Group 0 interrupts. 187 */ 188 #define ARM_G1S_IRQ_PROPS(grp) \ 189 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 190 GIC_INTR_CFG_LEVEL), \ 191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 192 GIC_INTR_CFG_EDGE), \ 193 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 194 GIC_INTR_CFG_EDGE), \ 195 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 196 GIC_INTR_CFG_EDGE), \ 197 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 198 GIC_INTR_CFG_EDGE), \ 199 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 200 GIC_INTR_CFG_EDGE), \ 201 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 202 GIC_INTR_CFG_EDGE) 203 204 #define ARM_G0_IRQ_PROPS(grp) \ 205 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ 206 GIC_INTR_CFG_EDGE), \ 207 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 208 GIC_INTR_CFG_EDGE) 209 210 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ 211 ARM_SHARED_RAM_BASE, \ 212 ARM_SHARED_RAM_SIZE, \ 213 MT_DEVICE | MT_RW | MT_SECURE) 214 215 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 216 ARM_NS_DRAM1_BASE, \ 217 ARM_NS_DRAM1_SIZE, \ 218 MT_MEMORY | MT_RW | MT_NS) 219 220 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ 221 ARM_DRAM2_BASE, \ 222 ARM_DRAM2_SIZE, \ 223 MT_MEMORY | MT_RW | MT_NS) 224 #ifdef SPD_tspd 225 226 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ 227 TSP_SEC_MEM_BASE, \ 228 TSP_SEC_MEM_SIZE, \ 229 MT_MEMORY | MT_RW | MT_SECURE) 230 #endif 231 232 #if ARM_BL31_IN_DRAM 233 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ 234 BL31_BASE, \ 235 PLAT_ARM_MAX_BL31_SIZE, \ 236 MT_MEMORY | MT_RW | MT_SECURE) 237 #endif 238 239 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ 240 ARM_EL3_TZC_DRAM1_BASE, \ 241 ARM_EL3_TZC_DRAM1_SIZE, \ 242 MT_MEMORY | MT_RW | MT_SECURE) 243 244 /* 245 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section 246 * otherwise one region is defined containing both. 247 */ 248 #if SEPARATE_CODE_AND_RODATA 249 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 250 BL_CODE_BASE, \ 251 BL_CODE_END - BL_CODE_BASE, \ 252 MT_CODE | MT_SECURE), \ 253 MAP_REGION_FLAT( \ 254 BL_RO_DATA_BASE, \ 255 BL_RO_DATA_END \ 256 - BL_RO_DATA_BASE, \ 257 MT_RO_DATA | MT_SECURE) 258 #else 259 #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ 260 BL_CODE_BASE, \ 261 BL_CODE_END - BL_CODE_BASE, \ 262 MT_CODE | MT_SECURE) 263 #endif 264 #if USE_COHERENT_MEM 265 #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 266 BL_COHERENT_RAM_BASE, \ 267 BL_COHERENT_RAM_END \ 268 - BL_COHERENT_RAM_BASE, \ 269 MT_DEVICE | MT_RW | MT_SECURE) 270 #endif 271 #if USE_ROMLIB 272 #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ 273 ROMLIB_RO_BASE, \ 274 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ 275 MT_CODE | MT_SECURE) 276 277 #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ 278 ROMLIB_RW_BASE, \ 279 ROMLIB_RW_END - ROMLIB_RW_BASE,\ 280 MT_MEMORY | MT_RW | MT_SECURE) 281 #endif 282 283 /* 284 * The max number of regions like RO(code), coherent and data required by 285 * different BL stages which need to be mapped in the MMU. 286 */ 287 # define ARM_BL_REGIONS 4 288 289 #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ 290 ARM_BL_REGIONS) 291 292 /* Memory mapped Generic timer interfaces */ 293 #define ARM_SYS_CNTCTL_BASE 0x2a430000 294 #define ARM_SYS_CNTREAD_BASE 0x2a800000 295 #define ARM_SYS_TIMCTL_BASE 0x2a810000 296 #define ARM_SYS_CNT_BASE_S 0x2a820000 297 #define ARM_SYS_CNT_BASE_NS 0x2a830000 298 299 #define ARM_CONSOLE_BAUDRATE 115200 300 301 /* Trusted Watchdog constants */ 302 #define ARM_SP805_TWDG_BASE 0x2a490000 303 #define ARM_SP805_TWDG_CLK_HZ 32768 304 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 305 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ 306 #define ARM_TWDG_TIMEOUT_SEC 128 307 #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ 308 ARM_TWDG_TIMEOUT_SEC) 309 310 /****************************************************************************** 311 * Required platform porting definitions common to all ARM standard platforms 312 *****************************************************************************/ 313 314 /* 315 * We need to access DRAM2 from BL2 for PSCI_MEM_PROTECT for 316 * AArch64 builds 317 */ 318 #ifdef AARCH64 319 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 320 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 321 #else 322 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 323 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 324 #endif 325 326 327 /* 328 * This macro defines the deepest retention state possible. A higher state 329 * id will represent an invalid or a power down state. 330 */ 331 #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET 332 333 /* 334 * This macro defines the deepest power down states possible. Any state ID 335 * higher than this is invalid. 336 */ 337 #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF 338 339 /* 340 * Some data must be aligned on the biggest cache line size in the platform. 341 * This is known only to the platform as it might have a combination of 342 * integrated and external caches. 343 */ 344 #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) 345 346 /* 347 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base 348 * and limit. Leave enough space of BL2 meminfo. 349 */ 350 #define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t) 351 #define ARM_TB_FW_CONFIG_LIMIT ARM_BL_RAM_BASE + PAGE_SIZE 352 353 /******************************************************************************* 354 * BL1 specific defines. 355 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of 356 * addresses. 357 ******************************************************************************/ 358 #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE 359 #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ 360 + (PLAT_ARM_TRUSTED_ROM_SIZE - \ 361 PLAT_ARM_MAX_ROMLIB_RO_SIZE)) 362 /* 363 * Put BL1 RW at the top of the Trusted SRAM. 364 */ 365 #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ 366 ARM_BL_RAM_SIZE - \ 367 (PLAT_ARM_MAX_BL1_RW_SIZE +\ 368 PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 369 #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ 370 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) 371 372 #define ROMLIB_RO_BASE BL1_RO_LIMIT 373 #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) 374 375 #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) 376 #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) 377 378 /******************************************************************************* 379 * BL2 specific defines. 380 ******************************************************************************/ 381 #if BL2_AT_EL3 382 /* Put BL2 towards the middle of the Trusted SRAM */ 383 #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ 384 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) 385 #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 386 387 #else 388 /* 389 * Put BL2 just below BL1. 390 */ 391 #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) 392 #define BL2_LIMIT BL1_RW_BASE 393 #endif 394 395 /******************************************************************************* 396 * BL31 specific defines. 397 ******************************************************************************/ 398 #if ARM_BL31_IN_DRAM 399 /* 400 * Put BL31 at the bottom of TZC secured DRAM 401 */ 402 #define BL31_BASE ARM_AP_TZC_DRAM1_BASE 403 #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 404 PLAT_ARM_MAX_BL31_SIZE) 405 #elif (RESET_TO_BL31) 406 /* 407 * Put BL31_BASE in the middle of the Trusted SRAM. 408 */ 409 #define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \ 410 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1)) 411 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 412 #else 413 /* Put BL31 below BL2 in the Trusted SRAM.*/ 414 #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 415 - PLAT_ARM_MAX_BL31_SIZE) 416 #define BL31_PROGBITS_LIMIT BL2_BASE 417 /* 418 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is 419 * because in the BL2_AT_EL3 configuration, BL2 is always resident. 420 */ 421 #if BL2_AT_EL3 422 #define BL31_LIMIT BL2_BASE 423 #else 424 #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 425 #endif 426 #endif 427 428 #if defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME 429 /******************************************************************************* 430 * BL32 specific defines for EL3 runtime in AArch32 mode 431 ******************************************************************************/ 432 # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME 433 /* 434 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding 435 * the page reserved for fw_configs) to BL32 436 */ 437 # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT 438 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 439 # else 440 /* Put BL32 below BL2 in the Trusted SRAM.*/ 441 # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ 442 - PLAT_ARM_MAX_BL32_SIZE) 443 # define BL32_PROGBITS_LIMIT BL2_BASE 444 # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) 445 # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ 446 447 #else 448 /******************************************************************************* 449 * BL32 specific defines for EL3 runtime in AArch64 mode 450 ******************************************************************************/ 451 /* 452 * On ARM standard platforms, the TSP can execute from Trusted SRAM, 453 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone 454 * controller. 455 */ 456 # if ENABLE_SPM 457 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 458 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) 459 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) 460 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 461 ARM_AP_TZC_DRAM1_SIZE) 462 # elif ARM_BL31_IN_DRAM 463 # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ 464 PLAT_ARM_MAX_BL31_SIZE) 465 # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ 466 PLAT_ARM_MAX_BL31_SIZE) 467 # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ 468 PLAT_ARM_MAX_BL31_SIZE) 469 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 470 ARM_AP_TZC_DRAM1_SIZE) 471 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID 472 # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE 473 # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE 474 # define TSP_PROGBITS_LIMIT BL31_BASE 475 # define BL32_BASE ARM_TB_FW_CONFIG_LIMIT 476 # define BL32_LIMIT BL31_BASE 477 # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID 478 # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE 479 # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE 480 # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE 481 # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ 482 + (1 << 21)) 483 # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID 484 # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE 485 # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE 486 # define BL32_BASE ARM_AP_TZC_DRAM1_BASE 487 # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ 488 ARM_AP_TZC_DRAM1_SIZE) 489 # else 490 # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" 491 # endif 492 #endif /* AARCH32 || JUNO_AARCH32_EL3_RUNTIME */ 493 494 /* 495 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no 496 * SPD and no SPM, as they are the only ones that can be used as BL32. 497 */ 498 #if !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) 499 # if defined(SPD_none) && !ENABLE_SPM 500 # undef BL32_BASE 501 # endif /* defined(SPD_none) && !ENABLE_SPM */ 502 #endif /* !(defined(AARCH32) || JUNO_AARCH32_EL3_RUNTIME) */ 503 504 /******************************************************************************* 505 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. 506 ******************************************************************************/ 507 #define BL2U_BASE BL2_BASE 508 #define BL2U_LIMIT BL2_LIMIT 509 510 #define NS_BL2U_BASE ARM_NS_DRAM1_BASE 511 #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + 0x03EB8000) 512 513 /* 514 * ID of the secure physical generic timer interrupt used by the TSP. 515 */ 516 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 517 518 519 /* 520 * One cache line needed for bakery locks on ARM platforms 521 */ 522 #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) 523 524 /* Priority levels for ARM platforms */ 525 #define PLAT_RAS_PRI 0x10 526 #define PLAT_SDEI_CRITICAL_PRI 0x60 527 #define PLAT_SDEI_NORMAL_PRI 0x70 528 529 /* ARM platforms use 3 upper bits of secure interrupt priority */ 530 #define ARM_PRI_BITS 3 531 532 /* SGI used for SDEI signalling */ 533 #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 534 535 /* ARM SDEI dynamic private event numbers */ 536 #define ARM_SDEI_DP_EVENT_0 1000 537 #define ARM_SDEI_DP_EVENT_1 1001 538 #define ARM_SDEI_DP_EVENT_2 1002 539 540 /* ARM SDEI dynamic shared event numbers */ 541 #define ARM_SDEI_DS_EVENT_0 2000 542 #define ARM_SDEI_DS_EVENT_1 2001 543 #define ARM_SDEI_DS_EVENT_2 2002 544 545 #define ARM_SDEI_PRIVATE_EVENTS \ 546 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ 547 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 548 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 549 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 550 551 #define ARM_SDEI_SHARED_EVENTS \ 552 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 553 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ 554 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) 555 556 #endif /* ARM_DEF_H */ 557