1/* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30#ifndef __ARM_MACROS_S__ 31#define __ARM_MACROS_S__ 32 33#include <cci.h> 34#include <gic_v2.h> 35#include <platform_def.h> 36 37.section .rodata.gic_reg_name, "aS" 38gicc_regs: 39 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 40gicd_pend_reg: 41 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 42 " Offset:\t\t\tvalue\n" 43newline: 44 .asciz "\n" 45spacer: 46 .asciz ":\t\t0x" 47 48 /* --------------------------------------------- 49 * The below utility macro prints out relevant GIC 50 * registers whenever an unhandled exception is 51 * taken in BL3-1 on ARM standard platforms. 52 * Expects: GICD base in x16, GICC base in x17 53 * Clobbers: x0 - x10, sp 54 * --------------------------------------------- 55 */ 56 .macro arm_print_gic_regs 57 /* Load the gicc reg list to x6 */ 58 adr x6, gicc_regs 59 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 60 ldr w8, [x17, #GICC_HPPIR] 61 ldr w9, [x17, #GICC_AHPPIR] 62 ldr w10, [x17, #GICC_CTLR] 63 /* Store to the crash buf and print to console */ 64 bl str_in_crash_buf_print 65 66 /* Print the GICD_ISPENDR regs */ 67 add x7, x16, #GICD_ISPENDR 68 adr x4, gicd_pend_reg 69 bl asm_print_str 70gicd_ispendr_loop: 71 sub x4, x7, x16 72 cmp x4, #0x280 73 b.eq exit_print_gic_regs 74 bl asm_print_hex 75 76 adr x4, spacer 77 bl asm_print_str 78 79 ldr x4, [x7], #8 80 bl asm_print_hex 81 82 adr x4, newline 83 bl asm_print_str 84 b gicd_ispendr_loop 85exit_print_gic_regs: 86 .endm 87 88 89.section .rodata.cci_reg_name, "aS" 90cci_iface_regs: 91 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , "" 92 93 /* ------------------------------------------------ 94 * The below required platform porting macro prints 95 * out relevant interconnect registers whenever an 96 * unhandled exception is taken in BL3-1. 97 * Clobbers: x0 - x9, sp 98 * ------------------------------------------------ 99 */ 100 .macro plat_print_interconnect_regs 101 adr x6, cci_iface_regs 102 /* Store in x7 the base address of the first interface */ 103 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ 104 PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX)) 105 ldr w8, [x7, #SNOOP_CTRL_REG] 106 /* Store in x7 the base address of the second interface */ 107 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \ 108 PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX)) 109 ldr w9, [x7, #SNOOP_CTRL_REG] 110 /* Store to the crash buf and print to console */ 111 bl str_in_crash_buf_print 112 .endm 113 114 115#endif /* __ARM_MACROS_S__ */ 116