1b4315306SDan Handley/* 26355f234SVikram Kanigiri * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley#ifndef __ARM_MACROS_S__ 7b4315306SDan Handley#define __ARM_MACROS_S__ 8b4315306SDan Handley 9f14d1886SSoby Mathew#include <gic_common.h> 10f14d1886SSoby Mathew#include <gicv2.h> 11f14d1886SSoby Mathew#include <gicv3.h> 12b4315306SDan Handley#include <platform_def.h> 13b4315306SDan Handley 14b4315306SDan Handley.section .rodata.gic_reg_name, "aS" 15f14d1886SSoby Mathew/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */ 16b4315306SDan Handleygicc_regs: 17b4315306SDan Handley .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" 18f14d1886SSoby Mathew 19f14d1886SSoby Mathew/* Applicable only to GICv3 with SRE enabled */ 20f14d1886SSoby Mathewicc_regs: 21f14d1886SSoby Mathew .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", "" 22f14d1886SSoby Mathew 23f14d1886SSoby Mathew/* Registers common to both GICv2 and GICv3 */ 24b4315306SDan Handleygicd_pend_reg: 25b4315306SDan Handley .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \ 26b4315306SDan Handley " Offset:\t\t\tvalue\n" 27b4315306SDan Handleynewline: 28b4315306SDan Handley .asciz "\n" 29b4315306SDan Handleyspacer: 30b4315306SDan Handley .asciz ":\t\t0x" 31b4315306SDan Handley 32b4315306SDan Handley /* --------------------------------------------- 33b4315306SDan Handley * The below utility macro prints out relevant GIC 34b4315306SDan Handley * registers whenever an unhandled exception is 35d178637dSJuan Castillo * taken in BL31 on ARM standard platforms. 36b4315306SDan Handley * Expects: GICD base in x16, GICC base in x17 37b4315306SDan Handley * Clobbers: x0 - x10, sp 38b4315306SDan Handley * --------------------------------------------- 39b4315306SDan Handley */ 40b4315306SDan Handley .macro arm_print_gic_regs 41f14d1886SSoby Mathew /* Check for GICv3 system register access */ 42f14d1886SSoby Mathew mrs x7, id_aa64pfr0_el1 43f14d1886SSoby Mathew ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH 44f14d1886SSoby Mathew cmp x7, #1 45f14d1886SSoby Mathew b.ne print_gicv2 46f14d1886SSoby Mathew 47f14d1886SSoby Mathew /* Check for SRE enable */ 48f14d1886SSoby Mathew mrs x8, ICC_SRE_EL3 49f14d1886SSoby Mathew tst x8, #ICC_SRE_SRE_BIT 50f14d1886SSoby Mathew b.eq print_gicv2 51f14d1886SSoby Mathew 52f14d1886SSoby Mathew /* Load the icc reg list to x6 */ 53f14d1886SSoby Mathew adr x6, icc_regs 54f14d1886SSoby Mathew /* Load the icc regs to gp regs used by str_in_crash_buf_print */ 55f14d1886SSoby Mathew mrs x8, ICC_HPPIR0_EL1 56f14d1886SSoby Mathew mrs x9, ICC_HPPIR1_EL1 57f14d1886SSoby Mathew mrs x10, ICC_CTLR_EL3 58f14d1886SSoby Mathew /* Store to the crash buf and print to console */ 59f14d1886SSoby Mathew bl str_in_crash_buf_print 60f14d1886SSoby Mathew b print_gic_common 61f14d1886SSoby Mathew 62f14d1886SSoby Mathewprint_gicv2: 63b4315306SDan Handley /* Load the gicc reg list to x6 */ 64b4315306SDan Handley adr x6, gicc_regs 65b4315306SDan Handley /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ 66b4315306SDan Handley ldr w8, [x17, #GICC_HPPIR] 67b4315306SDan Handley ldr w9, [x17, #GICC_AHPPIR] 68b4315306SDan Handley ldr w10, [x17, #GICC_CTLR] 69b4315306SDan Handley /* Store to the crash buf and print to console */ 70b4315306SDan Handley bl str_in_crash_buf_print 71b4315306SDan Handley 72f14d1886SSoby Mathewprint_gic_common: 73b4315306SDan Handley /* Print the GICD_ISPENDR regs */ 74b4315306SDan Handley add x7, x16, #GICD_ISPENDR 75b4315306SDan Handley adr x4, gicd_pend_reg 76b4315306SDan Handley bl asm_print_str 77b4315306SDan Handleygicd_ispendr_loop: 78b4315306SDan Handley sub x4, x7, x16 79b4315306SDan Handley cmp x4, #0x280 80b4315306SDan Handley b.eq exit_print_gic_regs 81b4315306SDan Handley bl asm_print_hex 82b4315306SDan Handley 83b4315306SDan Handley adr x4, spacer 84b4315306SDan Handley bl asm_print_str 85b4315306SDan Handley 86b4315306SDan Handley ldr x4, [x7], #8 87b4315306SDan Handley bl asm_print_hex 88b4315306SDan Handley 89b4315306SDan Handley adr x4, newline 90b4315306SDan Handley bl asm_print_str 91b4315306SDan Handley b gicd_ispendr_loop 92b4315306SDan Handleyexit_print_gic_regs: 93b4315306SDan Handley .endm 94b4315306SDan Handley 95b4315306SDan Handley#endif /* __ARM_MACROS_S__ */ 96