xref: /rk3399_ARM-atf/include/plat/arm/board/common/v2m_def.h (revision b49b3221900e4bc1d223227273815492da599f20)
1b4315306SDan Handley /*
2b4315306SDan Handley  * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3b4315306SDan Handley  *
4b4315306SDan Handley  * Redistribution and use in source and binary forms, with or without
5b4315306SDan Handley  * modification, are permitted provided that the following conditions are met:
6b4315306SDan Handley  *
7b4315306SDan Handley  * Redistributions of source code must retain the above copyright notice, this
8b4315306SDan Handley  * list of conditions and the following disclaimer.
9b4315306SDan Handley  *
10b4315306SDan Handley  * Redistributions in binary form must reproduce the above copyright notice,
11b4315306SDan Handley  * this list of conditions and the following disclaimer in the documentation
12b4315306SDan Handley  * and/or other materials provided with the distribution.
13b4315306SDan Handley  *
14b4315306SDan Handley  * Neither the name of ARM nor the names of its contributors may be used
15b4315306SDan Handley  * to endorse or promote products derived from this software without specific
16b4315306SDan Handley  * prior written permission.
17b4315306SDan Handley  *
18b4315306SDan Handley  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19b4315306SDan Handley  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20b4315306SDan Handley  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21b4315306SDan Handley  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22b4315306SDan Handley  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23b4315306SDan Handley  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24b4315306SDan Handley  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25b4315306SDan Handley  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26b4315306SDan Handley  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27b4315306SDan Handley  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28b4315306SDan Handley  * POSSIBILITY OF SUCH DAMAGE.
29b4315306SDan Handley  */
30b4315306SDan Handley #ifndef __V2M_DEF_H__
31b4315306SDan Handley #define __V2M_DEF_H__
32b4315306SDan Handley 
33b4315306SDan Handley #include <xlat_tables.h>
34b4315306SDan Handley 
35b4315306SDan Handley 
36b4315306SDan Handley /* V2M motherboard system registers & offsets */
37b4315306SDan Handley #define V2M_SYSREGS_BASE		0x1c010000
38b4315306SDan Handley #define V2M_SYS_ID			0x0
39b4315306SDan Handley #define V2M_SYS_SWITCH			0x4
40b4315306SDan Handley #define V2M_SYS_LED			0x8
41b4315306SDan Handley #define V2M_SYS_CFGDATA			0xa0
42b4315306SDan Handley #define V2M_SYS_CFGCTRL			0xa4
43b4315306SDan Handley #define V2M_SYS_CFGSTATUS		0xa8
44b4315306SDan Handley 
45b4315306SDan Handley #define V2M_CFGCTRL_START		(1 << 31)
46b4315306SDan Handley #define V2M_CFGCTRL_RW			(1 << 30)
47b4315306SDan Handley #define V2M_CFGCTRL_FUNC_SHIFT		20
48b4315306SDan Handley #define V2M_CFGCTRL_FUNC(fn)		(fn << V2M_CFGCTRL_FUNC_SHIFT)
49b4315306SDan Handley #define V2M_FUNC_CLK_GEN		0x01
50b4315306SDan Handley #define V2M_FUNC_TEMP			0x04
51b4315306SDan Handley #define V2M_FUNC_DB_RESET		0x05
52b4315306SDan Handley #define V2M_FUNC_SCC_CFG		0x06
53b4315306SDan Handley #define V2M_FUNC_SHUTDOWN		0x08
54b4315306SDan Handley #define V2M_FUNC_REBOOT			0x09
55b4315306SDan Handley 
56b4315306SDan Handley /*
57b4315306SDan Handley  * V2M sysled bit definitions. The values written to this
58b4315306SDan Handley  * register are defined in arch.h & runtime_svc.h. Only
59b4315306SDan Handley  * used by the primary cpu to diagnose any cold boot issues.
60b4315306SDan Handley  *
61b4315306SDan Handley  * SYS_LED[0]   - Security state (S=0/NS=1)
62b4315306SDan Handley  * SYS_LED[2:1] - Exception Level (EL3-EL0)
63b4315306SDan Handley  * SYS_LED[7:3] - Exception Class (Sync/Async & origin)
64b4315306SDan Handley  *
65b4315306SDan Handley  */
66b4315306SDan Handley #define V2M_SYS_LED_SS_SHIFT		0x0
67b4315306SDan Handley #define V2M_SYS_LED_EL_SHIFT		0x1
68b4315306SDan Handley #define V2M_SYS_LED_EC_SHIFT		0x3
69b4315306SDan Handley 
70b4315306SDan Handley #define V2M_SYS_LED_SS_MASK		0x1
71b4315306SDan Handley #define V2M_SYS_LED_EL_MASK		0x3
72b4315306SDan Handley #define V2M_SYS_LED_EC_MASK		0x1f
73b4315306SDan Handley 
74b4315306SDan Handley /* V2M sysid register bits */
75b4315306SDan Handley #define V2M_SYS_ID_REV_SHIFT		28
76b4315306SDan Handley #define V2M_SYS_ID_HBI_SHIFT		16
77b4315306SDan Handley #define V2M_SYS_ID_BLD_SHIFT		12
78b4315306SDan Handley #define V2M_SYS_ID_ARCH_SHIFT		8
79b4315306SDan Handley #define V2M_SYS_ID_FPGA_SHIFT		0
80b4315306SDan Handley 
81b4315306SDan Handley #define V2M_SYS_ID_REV_MASK		0xf
82b4315306SDan Handley #define V2M_SYS_ID_HBI_MASK		0xfff
83b4315306SDan Handley #define V2M_SYS_ID_BLD_MASK		0xf
84b4315306SDan Handley #define V2M_SYS_ID_ARCH_MASK		0xf
85b4315306SDan Handley #define V2M_SYS_ID_FPGA_MASK		0xff
86b4315306SDan Handley 
87b4315306SDan Handley #define V2M_SYS_ID_BLD_LENGTH		4
88b4315306SDan Handley 
89b4315306SDan Handley 
90b4315306SDan Handley /* NOR Flash */
91b4315306SDan Handley #define V2M_FLASH0_BASE			0x08000000
92b4315306SDan Handley #define V2M_FLASH0_SIZE			0x04000000
93b4315306SDan Handley 
94b4315306SDan Handley #define V2M_IOFPGA_BASE			0x1c000000
95b4315306SDan Handley #define V2M_IOFPGA_SIZE			0x03000000
96b4315306SDan Handley 
97b4315306SDan Handley /* PL011 UART related constants */
98b4315306SDan Handley #define V2M_IOFPGA_UART0_BASE		0x1c090000
99b4315306SDan Handley #define V2M_IOFPGA_UART1_BASE		0x1c0a0000
100b4315306SDan Handley #define V2M_IOFPGA_UART2_BASE		0x1c0b0000
101b4315306SDan Handley #define V2M_IOFPGA_UART3_BASE		0x1c0c0000
102b4315306SDan Handley 
103b4315306SDan Handley #define V2M_IOFPGA_UART0_CLK_IN_HZ	24000000
104b4315306SDan Handley #define V2M_IOFPGA_UART1_CLK_IN_HZ	24000000
105b4315306SDan Handley #define V2M_IOFPGA_UART2_CLK_IN_HZ	24000000
106b4315306SDan Handley #define V2M_IOFPGA_UART3_CLK_IN_HZ	24000000
107b4315306SDan Handley 
108*b49b3221SRyan Harkin /* SP804 timer related constants */
109*b49b3221SRyan Harkin #define V2M_SP804_TIMER0_BASE		0x1C110000
110*b49b3221SRyan Harkin #define V2M_SP804_TIMER1_BASE		0x1C120000
111b4315306SDan Handley 
112b4315306SDan Handley #define V2M_MAP_FLASH0			MAP_REGION_FLAT(V2M_FLASH0_BASE,\
113b4315306SDan Handley 						V2M_FLASH0_SIZE,	\
114b4315306SDan Handley 						MT_MEMORY | MT_RO | MT_SECURE)
115b4315306SDan Handley 
116b4315306SDan Handley #define V2M_MAP_IOFPGA			MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
117b4315306SDan Handley 						V2M_IOFPGA_SIZE,		\
118b4315306SDan Handley 						MT_DEVICE | MT_RW | MT_SECURE)
119b4315306SDan Handley 
120b4315306SDan Handley 
121b4315306SDan Handley 
122b4315306SDan Handley #endif /* __V2M_DEF_H__ */
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