1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef BOARD_CSS_DEF_H 8 #define BOARD_CSS_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 #include <soc_css_def.h> 14 #include <v2m_def.h> 15 16 /* 17 * Definitions common to all ARM CSS-based development platforms 18 */ 19 20 /* Platform ID address */ 21 #define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 22 23 /* Platform ID related accessors */ 24 #define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f 25 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 26 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 27 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 28 #define BOARD_CSS_PLAT_TYPE_RTL 0x00 29 #define BOARD_CSS_PLAT_TYPE_FPGA 0x01 30 #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 31 #define BOARD_CSS_PLAT_TYPE_FVP 0x03 32 33 #ifndef __ASSEMBLY__ 34 35 #include <lib/mmio.h> 36 37 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 38 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 39 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 40 41 #endif /* __ASSEMBLY__ */ 42 43 44 #define MAX_IO_DEVICES 3 45 #define MAX_IO_HANDLES 4 46 47 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 48 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 49 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 50 51 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 52 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 53 54 /* 55 * Required platform porting definitions common to all ARM CSS-based 56 * development platforms 57 */ 58 59 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 60 61 /* UART related constants */ 62 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 63 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 64 65 #define PLAT_ARM_BL31_RUN_UART_BASE SOC_CSS_UART1_BASE 66 #define PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 67 68 #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE 69 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 70 71 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE 72 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ 73 74 #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE 75 #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 76 77 #endif /* BOARD_CSS_DEF_H */ 78