1b4315306SDan Handley /* 2*ef1daa42SManish V Badarkhe * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3b4315306SDan Handley * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5b4315306SDan Handley */ 6b4315306SDan Handley 7c3cf06f1SAntonio Nino Diaz #ifndef BOARD_CSS_DEF_H 8c3cf06f1SAntonio Nino Diaz #define BOARD_CSS_DEF_H 9b4315306SDan Handley 1009d40e0eSAntonio Nino Diaz #include <lib/utils_def.h> 11bd9344f6SAntonio Nino Diaz #include <plat/arm/board/common/v2m_def.h> 12bd9344f6SAntonio Nino Diaz #include <plat/arm/soc/common/soc_css_def.h> 1309d40e0eSAntonio Nino Diaz #include <plat/common/common_def.h> 1409d40e0eSAntonio Nino Diaz 15b4315306SDan Handley /* 16b4315306SDan Handley * Definitions common to all ARM CSS-based development platforms 17b4315306SDan Handley */ 18b4315306SDan Handley 19b4315306SDan Handley /* Platform ID address */ 20b4315306SDan Handley #define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0 21b4315306SDan Handley 22b4315306SDan Handley /* Platform ID related accessors */ 23b4315306SDan Handley #define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f 24b4315306SDan Handley #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0 25b4315306SDan Handley #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00 26b4315306SDan Handley #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8 27b4315306SDan Handley #define BOARD_CSS_PLAT_TYPE_RTL 0x00 28b4315306SDan Handley #define BOARD_CSS_PLAT_TYPE_FPGA 0x01 29b4315306SDan Handley #define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02 30b4315306SDan Handley #define BOARD_CSS_PLAT_TYPE_FVP 0x03 31b4315306SDan Handley 32d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 33b4315306SDan Handley 3409d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 35b4315306SDan Handley 36b4315306SDan Handley #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 37b4315306SDan Handley ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 38b4315306SDan Handley >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 39b4315306SDan Handley 40d5dfdeb6SJulius Werner #endif /* __ASSEMBLER__ */ 41b4315306SDan Handley 42b4315306SDan Handley 430f58d4f2SAntonio Nino Diaz #define MAX_IO_DEVICES 3 440f58d4f2SAntonio Nino Diaz #define MAX_IO_HANDLES 4 450f58d4f2SAntonio Nino Diaz 460f58d4f2SAntonio Nino Diaz /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 4749e9ac28SManish V Badarkhe #define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE 4849e9ac28SManish V Badarkhe #define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 490f58d4f2SAntonio Nino Diaz 50*ef1daa42SManish V Badarkhe #if ARM_GPT_SUPPORT 51*ef1daa42SManish V Badarkhe /* 52*ef1daa42SManish V Badarkhe * Offset of the FIP in the GPT image. BL1 component uses this option 53*ef1daa42SManish V Badarkhe * as it does not load the partition table to get the FIP base 54*ef1daa42SManish V Badarkhe * address. At sector 34 by default (i.e. after reserved sectors 0-33) 55*ef1daa42SManish V Badarkhe * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400 56*ef1daa42SManish V Badarkhe */ 57*ef1daa42SManish V Badarkhe #define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400 58*ef1daa42SManish V Badarkhe #endif /* ARM_GPT_SUPPORT */ 59*ef1daa42SManish V Badarkhe 600f58d4f2SAntonio Nino Diaz #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 610f58d4f2SAntonio Nino Diaz #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 620f58d4f2SAntonio Nino Diaz 63b4315306SDan Handley /* UART related constants */ 64b4315306SDan Handley #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 65b4315306SDan Handley #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 66b4315306SDan Handley 670d28096cSUsama Arif #define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE 680d28096cSUsama Arif #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 69080225daSSoby Mathew 700d28096cSUsama Arif #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 710d28096cSUsama Arif #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 72b4315306SDan Handley 73b4315306SDan Handley #define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE 74b4315306SDan Handley #define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ 75b4315306SDan Handley 76c3cf06f1SAntonio Nino Diaz #endif /* BOARD_CSS_DEF_H */ 77