1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __XLAT_TABLES_DEFS_H__ 8 #define __XLAT_TABLES_DEFS_H__ 9 10 #include <utils_def.h> 11 12 /* Miscellaneous MMU related constants */ 13 #define NUM_2MB_IN_GB (U(1) << 9) 14 #define NUM_4K_IN_2MB (U(1) << 9) 15 #define NUM_GB_IN_4GB (U(1) << 2) 16 17 #define TWO_MB_SHIFT U(21) 18 #define ONE_GB_SHIFT U(30) 19 #define FOUR_KB_SHIFT U(12) 20 21 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 22 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 23 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 24 25 #define INVALID_DESC U(0x0) 26 #define BLOCK_DESC U(0x1) /* Table levels 0-2 */ 27 #define TABLE_DESC U(0x3) /* Table levels 0-2 */ 28 #define PAGE_DESC U(0x3) /* Table level 3 */ 29 #define DESC_MASK U(0x3) 30 31 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 32 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 33 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 34 35 /* XN: Translation regimes that support one VA range (EL2 and EL3). */ 36 #define XN (ULL(1) << 2) 37 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */ 38 #define UXN (ULL(1) << 2) 39 #define PXN (ULL(1) << 1) 40 #define CONT_HINT (ULL(1) << 0) 41 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 42 43 #define NON_GLOBAL (U(1) << 9) 44 #define ACCESS_FLAG (U(1) << 8) 45 #define NSH (U(0x0) << 6) 46 #define OSH (U(0x2) << 6) 47 #define ISH (U(0x3) << 6) 48 49 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) 50 51 /* 52 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or 53 * 64KB. However, TF only supports the 4KB case at the moment. 54 */ 55 #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT 56 #define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) 57 #define PAGE_SIZE_MASK (PAGE_SIZE - 1) 58 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) 59 60 #define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ 61 #define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) 62 63 #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ 64 #define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) 65 66 #define XLAT_TABLE_LEVEL_MAX U(3) 67 68 /* Values for number of entries in each MMU translation table */ 69 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 70 #define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) 71 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) 72 73 /* Values to convert a memory address to an index into a translation table */ 74 #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 75 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 76 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 77 #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 78 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ 79 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 80 81 #define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level)) 82 /* Mask to get the bits used to index inside a block of a certain level */ 83 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1) 84 /* Mask to get the address bits common to a block of a certain table level*/ 85 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 86 87 /* 88 * AP[1] bit is ignored by hardware and is 89 * treated as if it is One in EL2/EL3 90 */ 91 #define AP_RO (U(0x1) << 5) 92 #define AP_RW (U(0x0) << 5) 93 94 #define NS (U(0x1) << 3) 95 #define ATTR_NON_CACHEABLE_INDEX U(0x2) 96 #define ATTR_DEVICE_INDEX U(0x1) 97 #define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0) 98 #define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) 99 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 100 #define ATTR_NON_CACHEABLE U(0x44) 101 /* Device-nGnRE */ 102 #define ATTR_DEVICE U(0x4) 103 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 104 #define ATTR_IWBWA_OWBWA_NTR U(0xff) 105 #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 106 #define ATTR_INDEX_MASK U(0x3) 107 #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) 108 109 /* 110 * Flags to override default values used to program system registers while 111 * enabling the MMU. 112 */ 113 #define DISABLE_DCACHE (U(1) << 0) 114 115 /* 116 * This flag marks the translation tables are Non-cacheable for MMU accesses. 117 * If the flag is not specified, by default the tables are cacheable. 118 */ 119 #define XLAT_TABLE_NC (U(1) << 1) 120 121 #endif /* __XLAT_TABLES_DEFS_H__ */ 122