17bb01fb2SAntonio Nino Diaz /* 27bb01fb2SAntonio Nino Diaz * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 37bb01fb2SAntonio Nino Diaz * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57bb01fb2SAntonio Nino Diaz */ 67bb01fb2SAntonio Nino Diaz 77bb01fb2SAntonio Nino Diaz #ifndef __XLAT_TABLES_DEFS_H__ 87bb01fb2SAntonio Nino Diaz #define __XLAT_TABLES_DEFS_H__ 97bb01fb2SAntonio Nino Diaz 1053d9c9c8SScott Branden #include <utils_def.h> 117bb01fb2SAntonio Nino Diaz 127bb01fb2SAntonio Nino Diaz /* Miscellaneous MMU related constants */ 137bb01fb2SAntonio Nino Diaz #define NUM_2MB_IN_GB (1 << 9) 147bb01fb2SAntonio Nino Diaz #define NUM_4K_IN_2MB (1 << 9) 157bb01fb2SAntonio Nino Diaz #define NUM_GB_IN_4GB (1 << 2) 167bb01fb2SAntonio Nino Diaz 177bb01fb2SAntonio Nino Diaz #define TWO_MB_SHIFT 21 187bb01fb2SAntonio Nino Diaz #define ONE_GB_SHIFT 30 197bb01fb2SAntonio Nino Diaz #define FOUR_KB_SHIFT 12 207bb01fb2SAntonio Nino Diaz 217bb01fb2SAntonio Nino Diaz #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 227bb01fb2SAntonio Nino Diaz #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 237bb01fb2SAntonio Nino Diaz #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 247bb01fb2SAntonio Nino Diaz 257bb01fb2SAntonio Nino Diaz #define INVALID_DESC 0x0 267bb01fb2SAntonio Nino Diaz #define BLOCK_DESC 0x1 /* Table levels 0-2 */ 277bb01fb2SAntonio Nino Diaz #define TABLE_DESC 0x3 /* Table levels 0-2 */ 287bb01fb2SAntonio Nino Diaz #define PAGE_DESC 0x3 /* Table level 3 */ 297bb01fb2SAntonio Nino Diaz #define DESC_MASK 0x3 307bb01fb2SAntonio Nino Diaz 317bb01fb2SAntonio Nino Diaz #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 327bb01fb2SAntonio Nino Diaz #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 337bb01fb2SAntonio Nino Diaz #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 347bb01fb2SAntonio Nino Diaz 357bb01fb2SAntonio Nino Diaz #define XN (ULL(1) << 2) 367bb01fb2SAntonio Nino Diaz #define PXN (ULL(1) << 1) 377bb01fb2SAntonio Nino Diaz #define CONT_HINT (ULL(1) << 0) 387bb01fb2SAntonio Nino Diaz #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 397bb01fb2SAntonio Nino Diaz 407bb01fb2SAntonio Nino Diaz #define NON_GLOBAL (1 << 9) 417bb01fb2SAntonio Nino Diaz #define ACCESS_FLAG (1 << 8) 427bb01fb2SAntonio Nino Diaz #define NSH (0x0 << 6) 437bb01fb2SAntonio Nino Diaz #define OSH (0x2 << 6) 447bb01fb2SAntonio Nino Diaz #define ISH (0x3 << 6) 457bb01fb2SAntonio Nino Diaz 467bb01fb2SAntonio Nino Diaz #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) 477bb01fb2SAntonio Nino Diaz 487bb01fb2SAntonio Nino Diaz #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT /* 4, 16 or 64 KB */ 497bb01fb2SAntonio Nino Diaz #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) 507bb01fb2SAntonio Nino Diaz #define PAGE_SIZE_MASK (PAGE_SIZE - 1) 517bb01fb2SAntonio Nino Diaz #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) 527bb01fb2SAntonio Nino Diaz 537bb01fb2SAntonio Nino Diaz #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ 547bb01fb2SAntonio Nino Diaz #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) 557bb01fb2SAntonio Nino Diaz 567bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ 577bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) 587bb01fb2SAntonio Nino Diaz 597bb01fb2SAntonio Nino Diaz #ifdef AARCH32 607bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_LEVEL_MIN 1 617bb01fb2SAntonio Nino Diaz #else 627bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_LEVEL_MIN 0 637bb01fb2SAntonio Nino Diaz #endif /* AARCH32 */ 647bb01fb2SAntonio Nino Diaz 657bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_LEVEL_MAX 3 667bb01fb2SAntonio Nino Diaz 677bb01fb2SAntonio Nino Diaz /* Values for number of entries in each MMU translation table */ 687bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 697bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) 707bb01fb2SAntonio Nino Diaz #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) 717bb01fb2SAntonio Nino Diaz 727bb01fb2SAntonio Nino Diaz /* Values to convert a memory address to an index into a translation table */ 737bb01fb2SAntonio Nino Diaz #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 747bb01fb2SAntonio Nino Diaz #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 757bb01fb2SAntonio Nino Diaz #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 767bb01fb2SAntonio Nino Diaz #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 777bb01fb2SAntonio Nino Diaz #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ 787bb01fb2SAntonio Nino Diaz ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 797bb01fb2SAntonio Nino Diaz 807bb01fb2SAntonio Nino Diaz #define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level)) 817bb01fb2SAntonio Nino Diaz /* Mask to get the bits used to index inside a block of a certain level */ 827bb01fb2SAntonio Nino Diaz #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1) 837bb01fb2SAntonio Nino Diaz /* Mask to get the address bits common to a block of a certain table level*/ 847bb01fb2SAntonio Nino Diaz #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 857bb01fb2SAntonio Nino Diaz 867bb01fb2SAntonio Nino Diaz /* 877bb01fb2SAntonio Nino Diaz * AP[1] bit is ignored by hardware and is 887bb01fb2SAntonio Nino Diaz * treated as if it is One in EL2/EL3 897bb01fb2SAntonio Nino Diaz */ 907bb01fb2SAntonio Nino Diaz #define AP_RO (0x1 << 5) 917bb01fb2SAntonio Nino Diaz #define AP_RW (0x0 << 5) 927bb01fb2SAntonio Nino Diaz 937bb01fb2SAntonio Nino Diaz #define NS (0x1 << 3) 947bb01fb2SAntonio Nino Diaz #define ATTR_NON_CACHEABLE_INDEX 0x2 957bb01fb2SAntonio Nino Diaz #define ATTR_DEVICE_INDEX 0x1 967bb01fb2SAntonio Nino Diaz #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 977bb01fb2SAntonio Nino Diaz #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) 987bb01fb2SAntonio Nino Diaz /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 997bb01fb2SAntonio Nino Diaz #define ATTR_NON_CACHEABLE (0x44) 1007bb01fb2SAntonio Nino Diaz /* Device-nGnRE */ 1017bb01fb2SAntonio Nino Diaz #define ATTR_DEVICE (0x4) 1027bb01fb2SAntonio Nino Diaz /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 1037bb01fb2SAntonio Nino Diaz #define ATTR_IWBWA_OWBWA_NTR (0xff) 1047bb01fb2SAntonio Nino Diaz #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 1057bb01fb2SAntonio Nino Diaz #define ATTR_INDEX_MASK 0x3 1067bb01fb2SAntonio Nino Diaz #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) 1077bb01fb2SAntonio Nino Diaz 1087bb01fb2SAntonio Nino Diaz /* 1097bb01fb2SAntonio Nino Diaz * Flags to override default values used to program system registers while 1107bb01fb2SAntonio Nino Diaz * enabling the MMU. 1117bb01fb2SAntonio Nino Diaz */ 1127bb01fb2SAntonio Nino Diaz #define DISABLE_DCACHE (1 << 0) 1137bb01fb2SAntonio Nino Diaz 1145d21b037SSummer Qin /* 1155d21b037SSummer Qin * This flag marks the translation tables are Non-cacheable for MMU accesses. 1165d21b037SSummer Qin * If the flag is not specified, by default the tables are cacheable. 1175d21b037SSummer Qin */ 1185d21b037SSummer Qin #define XLAT_TABLE_NC (1 << 1) 1195d21b037SSummer Qin 1207bb01fb2SAntonio Nino Diaz #endif /* __XLAT_TABLES_DEFS_H__ */ 121