1 /* 2 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __XLAT_MMU_HELPERS_H__ 8 #define __XLAT_MMU_HELPERS_H__ 9 10 /* 11 * The following flags are passed to enable_mmu_xxx() to override the default 12 * values used to program system registers while enabling the MMU. 13 */ 14 15 /* 16 * When this flag is used, all data access to Normal memory from this EL and all 17 * Normal memory accesses to the translation tables of this EL are non-cacheable 18 * for all levels of data and unified cache until the caches are enabled by 19 * setting the bit SCTLR_ELx.C. 20 */ 21 #define DISABLE_DCACHE (U(1) << 0) 22 23 /* 24 * Mark the translation tables as non-cacheable for the MMU table walker, which 25 * is a different observer from the PE/CPU. If the flag is not specified, the 26 * tables are cacheable for the MMU table walker. 27 * 28 * Note that, as far as the PE/CPU observer is concerned, the attributes used 29 * are the ones specified in the translation tables themselves. The MAIR 30 * register specifies the cacheability through the field AttrIndx of the lower 31 * attributes of the translation tables. The shareability is specified in the SH 32 * field of the lower attributes. 33 * 34 * The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn 35 * and SHn of the TCR register to access the translation tables. 36 * 37 * The attributes specified in the TCR register and the tables can be different 38 * as there are no checks to prevent that. Special care must be taken to ensure 39 * that there aren't mismatches. The behaviour in that case is described in the 40 * sections 'Mismatched memory attributes' in the ARMv8 ARM. 41 */ 42 #define XLAT_TABLE_NC (U(1) << 1) 43 44 /* 45 * Offsets into a mmu_cfg_params array generated by setup_mmu_cfg(). All 46 * parameters are 64 bits wide. 47 */ 48 #define MMU_CFG_MAIR 0 49 #define MMU_CFG_TCR 1 50 #define MMU_CFG_TTBR0 2 51 #define MMU_CFG_PARAM_MAX 3 52 53 #ifndef __ASSEMBLY__ 54 55 #include <sys/types.h> 56 57 /* 58 * Return the values that the MMU configuration registers must contain for the 59 * specified translation context. `params` must be a pointer to array of size 60 * MMU_CFG_PARAM_MAX. 61 */ 62 void setup_mmu_cfg(uint64_t *params, unsigned int flags, 63 const uint64_t *base_table, unsigned long long max_pa, 64 uintptr_t max_va, int xlat_regime); 65 66 #ifdef AARCH32 67 /* AArch32 specific translation table API */ 68 void enable_mmu_secure(unsigned int flags); 69 70 void enable_mmu_direct(unsigned int flags); 71 #else 72 /* AArch64 specific translation table APIs */ 73 void enable_mmu_el1(unsigned int flags); 74 void enable_mmu_el3(unsigned int flags); 75 76 void enable_mmu_direct_el1(unsigned int flags); 77 void enable_mmu_direct_el3(unsigned int flags); 78 #endif /* AARCH32 */ 79 80 int xlat_arch_is_granule_size_supported(size_t size); 81 size_t xlat_arch_get_max_supported_granule_size(void); 82 83 #endif /* __ASSEMBLY__ */ 84 85 #endif /* __XLAT_MMU_HELPERS_H__ */ 86