17bb01fb2SAntonio Nino Diaz /* 2*883d1b5dSAntonio Nino Diaz * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. 37bb01fb2SAntonio Nino Diaz * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 57bb01fb2SAntonio Nino Diaz */ 67bb01fb2SAntonio Nino Diaz 77bb01fb2SAntonio Nino Diaz #ifndef __XLAT_MMU_HELPERS_H__ 87bb01fb2SAntonio Nino Diaz #define __XLAT_MMU_HELPERS_H__ 97bb01fb2SAntonio Nino Diaz 10*883d1b5dSAntonio Nino Diaz /* 11*883d1b5dSAntonio Nino Diaz * The following flags are passed to enable_mmu_xxx() to override the default 12*883d1b5dSAntonio Nino Diaz * values used to program system registers while enabling the MMU. 13*883d1b5dSAntonio Nino Diaz */ 14*883d1b5dSAntonio Nino Diaz 15*883d1b5dSAntonio Nino Diaz /* 16*883d1b5dSAntonio Nino Diaz * When this flag is used, all data access to Normal memory from this EL and all 17*883d1b5dSAntonio Nino Diaz * Normal memory accesses to the translation tables of this EL are non-cacheable 18*883d1b5dSAntonio Nino Diaz * for all levels of data and unified cache until the caches are enabled by 19*883d1b5dSAntonio Nino Diaz * setting the bit SCTLR_ELx.C. 20*883d1b5dSAntonio Nino Diaz */ 21*883d1b5dSAntonio Nino Diaz #define DISABLE_DCACHE (U(1) << 0) 22*883d1b5dSAntonio Nino Diaz 23*883d1b5dSAntonio Nino Diaz /* 24*883d1b5dSAntonio Nino Diaz * Mark the translation tables as non-cacheable for the MMU table walker, which 25*883d1b5dSAntonio Nino Diaz * is a different observer from the PE/CPU. If the flag is not specified, the 26*883d1b5dSAntonio Nino Diaz * tables are cacheable for the MMU table walker. 27*883d1b5dSAntonio Nino Diaz * 28*883d1b5dSAntonio Nino Diaz * Note that, as far as the PE/CPU observer is concerned, the attributes used 29*883d1b5dSAntonio Nino Diaz * are the ones specified in the translation tables themselves. The MAIR 30*883d1b5dSAntonio Nino Diaz * register specifies the cacheability through the field AttrIndx of the lower 31*883d1b5dSAntonio Nino Diaz * attributes of the translation tables. The shareability is specified in the SH 32*883d1b5dSAntonio Nino Diaz * field of the lower attributes. 33*883d1b5dSAntonio Nino Diaz * 34*883d1b5dSAntonio Nino Diaz * The MMU table walker uses the attributes specified in the fields ORGNn, IRGNn 35*883d1b5dSAntonio Nino Diaz * and SHn of the TCR register to access the translation tables. 36*883d1b5dSAntonio Nino Diaz * 37*883d1b5dSAntonio Nino Diaz * The attributes specified in the TCR register and the tables can be different 38*883d1b5dSAntonio Nino Diaz * as there are no checks to prevent that. Special care must be taken to ensure 39*883d1b5dSAntonio Nino Diaz * that there aren't mismatches. The behaviour in that case is described in the 40*883d1b5dSAntonio Nino Diaz * sections 'Mismatched memory attributes' in the ARMv8 ARM. 41*883d1b5dSAntonio Nino Diaz */ 42*883d1b5dSAntonio Nino Diaz #define XLAT_TABLE_NC (U(1) << 1) 43*883d1b5dSAntonio Nino Diaz 44*883d1b5dSAntonio Nino Diaz #ifndef __ASSEMBLY__ 45*883d1b5dSAntonio Nino Diaz 467bb01fb2SAntonio Nino Diaz #ifdef AARCH32 477bb01fb2SAntonio Nino Diaz /* AArch32 specific translation table API */ 48*883d1b5dSAntonio Nino Diaz void enable_mmu_secure(unsigned int flags); 497bb01fb2SAntonio Nino Diaz #else 507bb01fb2SAntonio Nino Diaz /* AArch64 specific translation table APIs */ 517bb01fb2SAntonio Nino Diaz void enable_mmu_el1(unsigned int flags); 527bb01fb2SAntonio Nino Diaz void enable_mmu_el3(unsigned int flags); 537bb01fb2SAntonio Nino Diaz #endif /* AARCH32 */ 547bb01fb2SAntonio Nino Diaz 55*883d1b5dSAntonio Nino Diaz #endif /* __ASSEMBLY__ */ 56*883d1b5dSAntonio Nino Diaz 577bb01fb2SAntonio Nino Diaz #endif /* __XLAT_MMU_HELPERS_H__ */ 58