1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_H 8 #define PSCI_H 9 10 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 11 12 #include <common/bl_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/psci/psci_lib.h> /* To maintain compatibility for SPDs */ 15 #include <lib/utils_def.h> 16 17 /******************************************************************************* 18 * Number of power domains whose state this PSCI implementation can track 19 ******************************************************************************/ 20 #ifdef PLAT_NUM_PWR_DOMAINS 21 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 22 #else 23 #define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) 24 #endif 25 26 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 27 PLATFORM_CORE_COUNT) 28 29 /* This is the power level corresponding to a CPU */ 30 #define PSCI_CPU_PWR_LVL U(0) 31 32 /* 33 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 34 * uses the old power_state parameter format which has 2 bits to specify the 35 * power level, this constant is defined to be 3. 36 */ 37 #define PSCI_MAX_PWR_LVL U(3) 38 39 /******************************************************************************* 40 * Defines for runtime services function ids 41 ******************************************************************************/ 42 #define PSCI_VERSION U(0x84000000) 43 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 44 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 45 #define PSCI_CPU_OFF U(0x84000002) 46 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 47 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 48 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 49 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 50 #define PSCI_MIG_AARCH32 U(0x84000005) 51 #define PSCI_MIG_AARCH64 U(0xc4000005) 52 #define PSCI_MIG_INFO_TYPE U(0x84000006) 53 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 54 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 55 #define PSCI_SYSTEM_OFF U(0x84000008) 56 #define PSCI_SYSTEM_RESET U(0x84000009) 57 #define PSCI_FEATURES U(0x8400000A) 58 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 59 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 60 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 61 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 62 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 63 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 64 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 65 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 66 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 67 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 68 #define PSCI_MEM_PROTECT U(0x84000013) 69 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 70 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 71 72 /* 73 * Number of PSCI calls (above) implemented 74 */ 75 #if ENABLE_PSCI_STAT 76 #define PSCI_NUM_CALLS U(22) 77 #else 78 #define PSCI_NUM_CALLS U(18) 79 #endif 80 81 /* The macros below are used to identify PSCI calls from the SMC function ID */ 82 #define PSCI_FID_MASK U(0xffe0) 83 #define PSCI_FID_VALUE U(0) 84 #define is_psci_fid(_fid) \ 85 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 86 87 /******************************************************************************* 88 * PSCI Migrate and friends 89 ******************************************************************************/ 90 #define PSCI_TOS_UP_MIG_CAP 0 91 #define PSCI_TOS_NOT_UP_MIG_CAP 1 92 #define PSCI_TOS_NOT_PRESENT_MP 2 93 94 /******************************************************************************* 95 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 96 ******************************************************************************/ 97 #define PSTATE_ID_SHIFT U(0) 98 99 #if PSCI_EXTENDED_STATE_ID 100 #define PSTATE_VALID_MASK U(0xB0000000) 101 #define PSTATE_TYPE_SHIFT U(30) 102 #define PSTATE_ID_MASK U(0xfffffff) 103 #else 104 #define PSTATE_VALID_MASK U(0xFCFE0000) 105 #define PSTATE_TYPE_SHIFT U(16) 106 #define PSTATE_PWR_LVL_SHIFT U(24) 107 #define PSTATE_ID_MASK U(0xffff) 108 #define PSTATE_PWR_LVL_MASK U(0x3) 109 110 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 111 PSTATE_PWR_LVL_MASK) 112 #define psci_make_powerstate(state_id, type, pwrlvl) \ 113 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 114 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 115 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 116 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 117 118 #define PSTATE_TYPE_STANDBY U(0x0) 119 #define PSTATE_TYPE_POWERDOWN U(0x1) 120 #define PSTATE_TYPE_MASK U(0x1) 121 122 /******************************************************************************* 123 * PSCI CPU_FEATURES feature flag specific defines 124 ******************************************************************************/ 125 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 126 #define FF_PSTATE_SHIFT U(1) 127 #define FF_PSTATE_ORIG U(0) 128 #define FF_PSTATE_EXTENDED U(1) 129 #if PSCI_EXTENDED_STATE_ID 130 #define FF_PSTATE FF_PSTATE_EXTENDED 131 #else 132 #define FF_PSTATE FF_PSTATE_ORIG 133 #endif 134 135 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 136 #define FF_MODE_SUPPORT_SHIFT U(0) 137 #define FF_SUPPORTS_OS_INIT_MODE U(1) 138 139 /******************************************************************************* 140 * PSCI version 141 ******************************************************************************/ 142 #define PSCI_MAJOR_VER (U(1) << 16) 143 #define PSCI_MINOR_VER U(0x1) 144 145 /******************************************************************************* 146 * PSCI error codes 147 ******************************************************************************/ 148 #define PSCI_E_SUCCESS 0 149 #define PSCI_E_NOT_SUPPORTED -1 150 #define PSCI_E_INVALID_PARAMS -2 151 #define PSCI_E_DENIED -3 152 #define PSCI_E_ALREADY_ON -4 153 #define PSCI_E_ON_PENDING -5 154 #define PSCI_E_INTERN_FAIL -6 155 #define PSCI_E_NOT_PRESENT -7 156 #define PSCI_E_DISABLED -8 157 #define PSCI_E_INVALID_ADDRESS -9 158 159 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 160 161 /* 162 * SYSTEM_RESET2 macros 163 */ 164 #define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) 165 #define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 166 #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 167 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) 168 169 #ifndef __ASSEMBLER__ 170 171 #include <stdint.h> 172 173 /* Function to help build the psci capabilities bitfield */ 174 175 static inline unsigned int define_psci_cap(unsigned int x) 176 { 177 return U(1) << (x & U(0x1f)); 178 } 179 180 181 /* Power state helper functions */ 182 183 static inline unsigned int psci_get_pstate_id(unsigned int power_state) 184 { 185 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK; 186 } 187 188 static inline unsigned int psci_get_pstate_type(unsigned int power_state) 189 { 190 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK; 191 } 192 193 static inline unsigned int psci_check_power_state(unsigned int power_state) 194 { 195 return ((power_state) & PSTATE_VALID_MASK); 196 } 197 198 /* 199 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 200 * CPU. The definitions of these states can be found in Section 5.7.1 in the 201 * PSCI specification (ARM DEN 0022C). 202 */ 203 typedef enum { 204 AFF_STATE_ON = U(0), 205 AFF_STATE_OFF = U(1), 206 AFF_STATE_ON_PENDING = U(2) 207 } aff_info_state_t; 208 209 /* 210 * These are the power states reported by PSCI_NODE_HW_STATE API for the 211 * specified CPU. The definitions of these states can be found in Section 5.15.3 212 * of PSCI specification (ARM DEN 0022C). 213 */ 214 #define HW_ON 0 215 #define HW_OFF 1 216 #define HW_STANDBY 2 217 218 /* 219 * Macro to represent invalid affinity level within PSCI. 220 */ 221 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 222 223 /* 224 * Type for representing the local power state at a particular level. 225 */ 226 typedef uint8_t plat_local_state_t; 227 228 /* The local state macro used to represent RUN state. */ 229 #define PSCI_LOCAL_STATE_RUN U(0) 230 231 /* 232 * Function to test whether the plat_local_state is RUN state 233 */ 234 static inline int is_local_state_run(unsigned int plat_local_state) 235 { 236 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0; 237 } 238 239 /* 240 * Function to test whether the plat_local_state is RETENTION state 241 */ 242 static inline int is_local_state_retn(unsigned int plat_local_state) 243 { 244 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) && 245 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0; 246 } 247 248 /* 249 * Function to test whether the plat_local_state is OFF state 250 */ 251 static inline int is_local_state_off(unsigned int plat_local_state) 252 { 253 return ((plat_local_state > PLAT_MAX_RET_STATE) && 254 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0; 255 } 256 257 /***************************************************************************** 258 * This data structure defines the representation of the power state parameter 259 * for its exchange between the generic PSCI code and the platform port. For 260 * example, it is used by the platform port to specify the requested power 261 * states during a power management operation. It is used by the generic code to 262 * inform the platform about the target power states that each level should 263 * enter. 264 ****************************************************************************/ 265 typedef struct psci_power_state { 266 /* 267 * The pwr_domain_state[] stores the local power state at each level 268 * for the CPU. 269 */ 270 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 271 } psci_power_state_t; 272 273 /******************************************************************************* 274 * Structure used to store per-cpu information relevant to the PSCI service. 275 * It is populated in the per-cpu data array. In return we get a guarantee that 276 * this information will not reside on a cache line shared with another cpu. 277 ******************************************************************************/ 278 typedef struct psci_cpu_data { 279 /* State as seen by PSCI Affinity Info API */ 280 aff_info_state_t aff_info_state; 281 282 /* 283 * Highest power level which takes part in a power management 284 * operation. 285 */ 286 unsigned int target_pwrlvl; 287 288 /* The local power state of this CPU */ 289 plat_local_state_t local_state; 290 } psci_cpu_data_t; 291 292 /******************************************************************************* 293 * Structure populated by platform specific code to export routines which 294 * perform common low level power management functions 295 ******************************************************************************/ 296 typedef struct plat_psci_ops { 297 void (*cpu_standby)(plat_local_state_t cpu_state); 298 int (*pwr_domain_on)(u_register_t mpidr); 299 void (*pwr_domain_off)(const psci_power_state_t *target_state); 300 void (*pwr_domain_suspend_pwrdown_early)( 301 const psci_power_state_t *target_state); 302 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 303 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 304 void (*pwr_domain_on_finish_late)( 305 const psci_power_state_t *target_state); 306 void (*pwr_domain_suspend_finish)( 307 const psci_power_state_t *target_state); 308 void __dead2 (*pwr_domain_pwr_down_wfi)( 309 const psci_power_state_t *target_state); 310 void __dead2 (*system_off)(void); 311 void __dead2 (*system_reset)(void); 312 int (*validate_power_state)(unsigned int power_state, 313 psci_power_state_t *req_state); 314 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 315 void (*get_sys_suspend_power_state)( 316 psci_power_state_t *req_state); 317 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 318 int pwrlvl); 319 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 320 unsigned int power_state, 321 psci_power_state_t *output_state); 322 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 323 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 324 int (*read_mem_protect)(int *val); 325 int (*write_mem_protect)(int val); 326 int (*system_reset2)(int is_vendor, 327 int reset_type, u_register_t cookie); 328 } plat_psci_ops_t; 329 330 /******************************************************************************* 331 * Function & Data prototypes 332 ******************************************************************************/ 333 unsigned int psci_version(void); 334 int psci_cpu_on(u_register_t target_cpu, 335 uintptr_t entrypoint, 336 u_register_t context_id); 337 int psci_cpu_suspend(unsigned int power_state, 338 uintptr_t entrypoint, 339 u_register_t context_id); 340 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 341 int psci_cpu_off(void); 342 int psci_affinity_info(u_register_t target_affinity, 343 unsigned int lowest_affinity_level); 344 int psci_migrate(u_register_t target_cpu); 345 int psci_migrate_info_type(void); 346 u_register_t psci_migrate_info_up_cpu(void); 347 int psci_node_hw_state(u_register_t target_cpu, 348 unsigned int power_level); 349 int psci_features(unsigned int psci_fid); 350 void __dead2 psci_power_down_wfi(void); 351 void psci_arch_setup(void); 352 353 #endif /*__ASSEMBLER__*/ 354 355 #endif /* PSCI_H */ 356