1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_H 8 #define PSCI_H 9 10 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 11 12 #include <common/bl_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/psci/psci_lib.h> /* To maintain compatibility for SPDs */ 15 #include <lib/utils_def.h> 16 17 /******************************************************************************* 18 * Number of power domains whose state this PSCI implementation can track 19 ******************************************************************************/ 20 #ifdef PLAT_NUM_PWR_DOMAINS 21 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 22 #else 23 #define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) 24 #endif 25 26 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 27 PLATFORM_CORE_COUNT) 28 29 /* This is the power level corresponding to a CPU */ 30 #define PSCI_CPU_PWR_LVL U(0) 31 32 /* 33 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 34 * uses the old power_state parameter format which has 2 bits to specify the 35 * power level, this constant is defined to be 3. 36 */ 37 #define PSCI_MAX_PWR_LVL U(3) 38 39 /******************************************************************************* 40 * Defines for runtime services function ids 41 ******************************************************************************/ 42 #define PSCI_VERSION U(0x84000000) 43 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 44 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 45 #define PSCI_CPU_OFF U(0x84000002) 46 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 47 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 48 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 49 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 50 #define PSCI_MIG_AARCH32 U(0x84000005) 51 #define PSCI_MIG_AARCH64 U(0xc4000005) 52 #define PSCI_MIG_INFO_TYPE U(0x84000006) 53 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 54 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 55 #define PSCI_SYSTEM_OFF U(0x84000008) 56 #define PSCI_SYSTEM_RESET U(0x84000009) 57 #define PSCI_FEATURES U(0x8400000A) 58 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 59 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 60 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 61 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 62 #define PSCI_SET_SUSPEND_MODE U(0x8400000F) 63 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 64 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 65 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 66 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 67 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 68 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 69 #define PSCI_MEM_PROTECT U(0x84000013) 70 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 71 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 72 73 /* 74 * Number of PSCI calls (above) implemented 75 */ 76 #if ENABLE_PSCI_STAT 77 #if PSCI_OS_INIT_MODE 78 #define PSCI_NUM_CALLS U(30) 79 #else 80 #define PSCI_NUM_CALLS U(29) 81 #endif 82 #else 83 #if PSCI_OS_INIT_MODE 84 #define PSCI_NUM_CALLS U(26) 85 #else 86 #define PSCI_NUM_CALLS U(25) 87 #endif 88 #endif 89 90 /* The macros below are used to identify PSCI calls from the SMC function ID */ 91 #define PSCI_FID_MASK U(0xffe0) 92 #define PSCI_FID_VALUE U(0) 93 #define is_psci_fid(_fid) \ 94 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 95 96 /******************************************************************************* 97 * PSCI Migrate and friends 98 ******************************************************************************/ 99 #define PSCI_TOS_UP_MIG_CAP 0 100 #define PSCI_TOS_NOT_UP_MIG_CAP 1 101 #define PSCI_TOS_NOT_PRESENT_MP 2 102 103 /******************************************************************************* 104 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 105 ******************************************************************************/ 106 #define PSTATE_ID_SHIFT U(0) 107 108 #if PSCI_EXTENDED_STATE_ID 109 #define PSTATE_VALID_MASK U(0xB0000000) 110 #define PSTATE_TYPE_SHIFT U(30) 111 #define PSTATE_ID_MASK U(0xfffffff) 112 #else 113 #define PSTATE_VALID_MASK U(0xFCFE0000) 114 #define PSTATE_TYPE_SHIFT U(16) 115 #define PSTATE_PWR_LVL_SHIFT U(24) 116 #define PSTATE_ID_MASK U(0xffff) 117 #define PSTATE_PWR_LVL_MASK U(0x3) 118 119 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 120 PSTATE_PWR_LVL_MASK) 121 #define psci_make_powerstate(state_id, type, pwrlvl) \ 122 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 123 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 124 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 125 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 126 127 #define PSTATE_TYPE_STANDBY U(0x0) 128 #define PSTATE_TYPE_POWERDOWN U(0x1) 129 #define PSTATE_TYPE_MASK U(0x1) 130 131 /******************************************************************************* 132 * PSCI CPU_FEATURES feature flag specific defines 133 ******************************************************************************/ 134 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 135 #define FF_PSTATE_SHIFT U(1) 136 #define FF_PSTATE_ORIG U(0) 137 #define FF_PSTATE_EXTENDED U(1) 138 #if PSCI_EXTENDED_STATE_ID 139 #define FF_PSTATE FF_PSTATE_EXTENDED 140 #else 141 #define FF_PSTATE FF_PSTATE_ORIG 142 #endif 143 144 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 145 #define FF_MODE_SUPPORT_SHIFT U(0) 146 #define FF_SUPPORTS_OS_INIT_MODE U(1) 147 148 /******************************************************************************* 149 * PSCI version 150 ******************************************************************************/ 151 #define PSCI_MAJOR_VER (U(1) << 16) 152 #define PSCI_MINOR_VER U(0x1) 153 154 /******************************************************************************* 155 * PSCI error codes 156 ******************************************************************************/ 157 #define PSCI_E_SUCCESS 0 158 #define PSCI_E_NOT_SUPPORTED -1 159 #define PSCI_E_INVALID_PARAMS -2 160 #define PSCI_E_DENIED -3 161 #define PSCI_E_ALREADY_ON -4 162 #define PSCI_E_ON_PENDING -5 163 #define PSCI_E_INTERN_FAIL -6 164 #define PSCI_E_NOT_PRESENT -7 165 #define PSCI_E_DISABLED -8 166 #define PSCI_E_INVALID_ADDRESS -9 167 168 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 169 170 /* 171 * SYSTEM_RESET2 macros 172 */ 173 #define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) 174 #define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 175 #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 176 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) 177 178 #ifndef __ASSEMBLER__ 179 180 #include <stdint.h> 181 182 /* Function to help build the psci capabilities bitfield */ 183 184 static inline unsigned int define_psci_cap(unsigned int x) 185 { 186 return U(1) << (x & U(0x1f)); 187 } 188 189 190 /* Power state helper functions */ 191 192 static inline unsigned int psci_get_pstate_id(unsigned int power_state) 193 { 194 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK; 195 } 196 197 static inline unsigned int psci_get_pstate_type(unsigned int power_state) 198 { 199 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK; 200 } 201 202 static inline unsigned int psci_check_power_state(unsigned int power_state) 203 { 204 return ((power_state) & PSTATE_VALID_MASK); 205 } 206 207 /* 208 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 209 * CPU. The definitions of these states can be found in Section 5.7.1 in the 210 * PSCI specification (ARM DEN 0022C). 211 */ 212 typedef enum { 213 AFF_STATE_ON = U(0), 214 AFF_STATE_OFF = U(1), 215 AFF_STATE_ON_PENDING = U(2) 216 } aff_info_state_t; 217 218 /* 219 * These are the power states reported by PSCI_NODE_HW_STATE API for the 220 * specified CPU. The definitions of these states can be found in Section 5.15.3 221 * of PSCI specification (ARM DEN 0022C). 222 */ 223 #define HW_ON 0 224 #define HW_OFF 1 225 #define HW_STANDBY 2 226 227 /* 228 * Macro to represent invalid affinity level within PSCI. 229 */ 230 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 231 232 /* 233 * Type for representing the local power state at a particular level. 234 */ 235 typedef uint8_t plat_local_state_t; 236 237 /* The local state macro used to represent RUN state. */ 238 #define PSCI_LOCAL_STATE_RUN U(0) 239 240 /* 241 * Function to test whether the plat_local_state is RUN state 242 */ 243 static inline int is_local_state_run(unsigned int plat_local_state) 244 { 245 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0; 246 } 247 248 /* 249 * Function to test whether the plat_local_state is RETENTION state 250 */ 251 static inline int is_local_state_retn(unsigned int plat_local_state) 252 { 253 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) && 254 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0; 255 } 256 257 /* 258 * Function to test whether the plat_local_state is OFF state 259 */ 260 static inline int is_local_state_off(unsigned int plat_local_state) 261 { 262 return ((plat_local_state > PLAT_MAX_RET_STATE) && 263 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0; 264 } 265 266 /***************************************************************************** 267 * This data structure defines the representation of the power state parameter 268 * for its exchange between the generic PSCI code and the platform port. For 269 * example, it is used by the platform port to specify the requested power 270 * states during a power management operation. It is used by the generic code to 271 * inform the platform about the target power states that each level should 272 * enter. 273 ****************************************************************************/ 274 typedef struct psci_power_state { 275 /* 276 * The pwr_domain_state[] stores the local power state at each level 277 * for the CPU. 278 */ 279 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 280 } psci_power_state_t; 281 282 /******************************************************************************* 283 * Structure used to store per-cpu information relevant to the PSCI service. 284 * It is populated in the per-cpu data array. In return we get a guarantee that 285 * this information will not reside on a cache line shared with another cpu. 286 ******************************************************************************/ 287 typedef struct psci_cpu_data { 288 /* State as seen by PSCI Affinity Info API */ 289 aff_info_state_t aff_info_state; 290 291 /* 292 * Highest power level which takes part in a power management 293 * operation. 294 */ 295 unsigned int target_pwrlvl; 296 297 /* The local power state of this CPU */ 298 plat_local_state_t local_state; 299 } psci_cpu_data_t; 300 301 /******************************************************************************* 302 * Structure populated by platform specific code to export routines which 303 * perform common low level power management functions 304 ******************************************************************************/ 305 typedef struct plat_psci_ops { 306 void (*cpu_standby)(plat_local_state_t cpu_state); 307 int (*pwr_domain_on)(u_register_t mpidr); 308 void (*pwr_domain_off)(const psci_power_state_t *target_state); 309 void (*pwr_domain_suspend_pwrdown_early)( 310 const psci_power_state_t *target_state); 311 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 312 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 313 void (*pwr_domain_on_finish_late)( 314 const psci_power_state_t *target_state); 315 void (*pwr_domain_suspend_finish)( 316 const psci_power_state_t *target_state); 317 void __dead2 (*pwr_domain_pwr_down_wfi)( 318 const psci_power_state_t *target_state); 319 void __dead2 (*system_off)(void); 320 void __dead2 (*system_reset)(void); 321 int (*validate_power_state)(unsigned int power_state, 322 psci_power_state_t *req_state); 323 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 324 void (*get_sys_suspend_power_state)( 325 psci_power_state_t *req_state); 326 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 327 int pwrlvl); 328 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 329 unsigned int power_state, 330 psci_power_state_t *output_state); 331 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 332 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 333 int (*read_mem_protect)(int *val); 334 int (*write_mem_protect)(int val); 335 int (*system_reset2)(int is_vendor, 336 int reset_type, u_register_t cookie); 337 } plat_psci_ops_t; 338 339 /******************************************************************************* 340 * Function & Data prototypes 341 ******************************************************************************/ 342 unsigned int psci_version(void); 343 int psci_cpu_on(u_register_t target_cpu, 344 uintptr_t entrypoint, 345 u_register_t context_id); 346 int psci_cpu_suspend(unsigned int power_state, 347 uintptr_t entrypoint, 348 u_register_t context_id); 349 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 350 int psci_cpu_off(void); 351 int psci_affinity_info(u_register_t target_affinity, 352 unsigned int lowest_affinity_level); 353 int psci_migrate(u_register_t target_cpu); 354 int psci_migrate_info_type(void); 355 u_register_t psci_migrate_info_up_cpu(void); 356 int psci_node_hw_state(u_register_t target_cpu, 357 unsigned int power_level); 358 int psci_features(unsigned int psci_fid); 359 #if PSCI_OS_INIT_MODE 360 int psci_set_suspend_mode(unsigned int mode); 361 #endif 362 void __dead2 psci_power_down_wfi(void); 363 void psci_arch_setup(void); 364 365 #endif /*__ASSEMBLER__*/ 366 367 #endif /* PSCI_H */ 368