1 /* 2 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PSCI_H 8 #define PSCI_H 9 10 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 11 12 #include <common/bl_common.h> 13 #include <lib/bakery_lock.h> 14 #include <lib/psci/psci_lib.h> /* To maintain compatibility for SPDs */ 15 #include <lib/utils_def.h> 16 17 /******************************************************************************* 18 * Number of power domains whose state this PSCI implementation can track 19 ******************************************************************************/ 20 #ifdef PLAT_NUM_PWR_DOMAINS 21 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 22 #else 23 #define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) 24 #endif 25 26 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 27 PLATFORM_CORE_COUNT) 28 29 /* This is the power level corresponding to a CPU */ 30 #define PSCI_CPU_PWR_LVL U(0) 31 32 /* 33 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 34 * uses the old power_state parameter format which has 2 bits to specify the 35 * power level, this constant is defined to be 3. 36 */ 37 #define PSCI_MAX_PWR_LVL U(3) 38 39 /******************************************************************************* 40 * Defines for runtime services function ids 41 ******************************************************************************/ 42 #define PSCI_VERSION U(0x84000000) 43 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 44 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 45 #define PSCI_CPU_OFF U(0x84000002) 46 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 47 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 48 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 49 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 50 #define PSCI_MIG_AARCH32 U(0x84000005) 51 #define PSCI_MIG_AARCH64 U(0xc4000005) 52 #define PSCI_MIG_INFO_TYPE U(0x84000006) 53 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 54 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 55 #define PSCI_SYSTEM_OFF U(0x84000008) 56 #define PSCI_SYSTEM_RESET U(0x84000009) 57 #define PSCI_FEATURES U(0x8400000A) 58 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 59 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 60 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 61 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 62 #define PSCI_SET_SUSPEND_MODE U(0x8400000F) 63 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 64 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 65 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 66 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 67 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 68 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 69 #define PSCI_MEM_PROTECT U(0x84000013) 70 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 71 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 72 73 /* 74 * Number of PSCI calls (above) implemented 75 */ 76 #if ENABLE_PSCI_STAT 77 #if PSCI_OS_INIT_MODE 78 #define PSCI_NUM_CALLS U(30) 79 #else 80 #define PSCI_NUM_CALLS U(29) 81 #endif 82 #else 83 #if PSCI_OS_INIT_MODE 84 #define PSCI_NUM_CALLS U(26) 85 #else 86 #define PSCI_NUM_CALLS U(25) 87 #endif 88 #endif 89 90 /* The macros below are used to identify PSCI calls from the SMC function ID */ 91 #define PSCI_FID_MASK U(0xffe0) 92 #define PSCI_FID_VALUE U(0) 93 #define is_psci_fid(_fid) \ 94 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 95 96 /******************************************************************************* 97 * PSCI Migrate and friends 98 ******************************************************************************/ 99 #define PSCI_TOS_UP_MIG_CAP 0 100 #define PSCI_TOS_NOT_UP_MIG_CAP 1 101 #define PSCI_TOS_NOT_PRESENT_MP 2 102 103 /******************************************************************************* 104 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 105 ******************************************************************************/ 106 #define PSTATE_ID_SHIFT U(0) 107 108 #if PSCI_EXTENDED_STATE_ID 109 #define PSTATE_VALID_MASK U(0xB0000000) 110 #define PSTATE_TYPE_SHIFT U(30) 111 #define PSTATE_ID_MASK U(0xfffffff) 112 #else 113 #define PSTATE_VALID_MASK U(0xFCFE0000) 114 #define PSTATE_TYPE_SHIFT U(16) 115 #define PSTATE_PWR_LVL_SHIFT U(24) 116 #define PSTATE_ID_MASK U(0xffff) 117 #define PSTATE_PWR_LVL_MASK U(0x3) 118 119 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 120 PSTATE_PWR_LVL_MASK) 121 #define psci_make_powerstate(state_id, type, pwrlvl) \ 122 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 123 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 124 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 125 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 126 127 #define PSTATE_TYPE_STANDBY U(0x0) 128 #define PSTATE_TYPE_POWERDOWN U(0x1) 129 #define PSTATE_TYPE_MASK U(0x1) 130 131 /******************************************************************************* 132 * PSCI CPU_FEATURES feature flag specific defines 133 ******************************************************************************/ 134 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 135 #define FF_PSTATE_SHIFT U(1) 136 #define FF_PSTATE_ORIG U(0) 137 #define FF_PSTATE_EXTENDED U(1) 138 #if PSCI_EXTENDED_STATE_ID 139 #define FF_PSTATE FF_PSTATE_EXTENDED 140 #else 141 #define FF_PSTATE FF_PSTATE_ORIG 142 #endif 143 144 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 145 #define FF_MODE_SUPPORT_SHIFT U(0) 146 #if PSCI_OS_INIT_MODE 147 #define FF_SUPPORTS_OS_INIT_MODE U(1) 148 #else 149 #define FF_SUPPORTS_OS_INIT_MODE U(0) 150 #endif 151 152 /******************************************************************************* 153 * PSCI version 154 ******************************************************************************/ 155 #define PSCI_MAJOR_VER (U(1) << 16) 156 #define PSCI_MINOR_VER U(0x1) 157 158 /******************************************************************************* 159 * PSCI error codes 160 ******************************************************************************/ 161 #define PSCI_E_SUCCESS 0 162 #define PSCI_E_NOT_SUPPORTED -1 163 #define PSCI_E_INVALID_PARAMS -2 164 #define PSCI_E_DENIED -3 165 #define PSCI_E_ALREADY_ON -4 166 #define PSCI_E_ON_PENDING -5 167 #define PSCI_E_INTERN_FAIL -6 168 #define PSCI_E_NOT_PRESENT -7 169 #define PSCI_E_DISABLED -8 170 #define PSCI_E_INVALID_ADDRESS -9 171 172 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 173 174 /* 175 * SYSTEM_RESET2 macros 176 */ 177 #define PSCI_RESET2_TYPE_VENDOR_SHIFT U(31) 178 #define PSCI_RESET2_TYPE_VENDOR (U(1) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 179 #define PSCI_RESET2_TYPE_ARCH (U(0) << PSCI_RESET2_TYPE_VENDOR_SHIFT) 180 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | U(0)) 181 182 #ifndef __ASSEMBLER__ 183 184 #include <stdint.h> 185 186 /* Function to help build the psci capabilities bitfield */ 187 188 static inline unsigned int define_psci_cap(unsigned int x) 189 { 190 return U(1) << (x & U(0x1f)); 191 } 192 193 194 /* Power state helper functions */ 195 196 static inline unsigned int psci_get_pstate_id(unsigned int power_state) 197 { 198 return ((power_state) >> PSTATE_ID_SHIFT) & PSTATE_ID_MASK; 199 } 200 201 static inline unsigned int psci_get_pstate_type(unsigned int power_state) 202 { 203 return ((power_state) >> PSTATE_TYPE_SHIFT) & PSTATE_TYPE_MASK; 204 } 205 206 static inline unsigned int psci_check_power_state(unsigned int power_state) 207 { 208 return ((power_state) & PSTATE_VALID_MASK); 209 } 210 211 /* 212 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 213 * CPU. The definitions of these states can be found in Section 5.7.1 in the 214 * PSCI specification (ARM DEN 0022C). 215 */ 216 typedef enum { 217 AFF_STATE_ON = U(0), 218 AFF_STATE_OFF = U(1), 219 AFF_STATE_ON_PENDING = U(2) 220 } aff_info_state_t; 221 222 /* 223 * These are the power states reported by PSCI_NODE_HW_STATE API for the 224 * specified CPU. The definitions of these states can be found in Section 5.15.3 225 * of PSCI specification (ARM DEN 0022C). 226 */ 227 #define HW_ON 0 228 #define HW_OFF 1 229 #define HW_STANDBY 2 230 231 /* 232 * Macro to represent invalid affinity level within PSCI. 233 */ 234 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 235 236 /* 237 * Type for representing the local power state at a particular level. 238 */ 239 typedef uint8_t plat_local_state_t; 240 241 /* The local state macro used to represent RUN state. */ 242 #define PSCI_LOCAL_STATE_RUN U(0) 243 244 /* 245 * Function to test whether the plat_local_state is RUN state 246 */ 247 static inline int is_local_state_run(unsigned int plat_local_state) 248 { 249 return (plat_local_state == PSCI_LOCAL_STATE_RUN) ? 1 : 0; 250 } 251 252 /* 253 * Function to test whether the plat_local_state is RETENTION state 254 */ 255 static inline int is_local_state_retn(unsigned int plat_local_state) 256 { 257 return ((plat_local_state > PSCI_LOCAL_STATE_RUN) && 258 (plat_local_state <= PLAT_MAX_RET_STATE)) ? 1 : 0; 259 } 260 261 /* 262 * Function to test whether the plat_local_state is OFF state 263 */ 264 static inline int is_local_state_off(unsigned int plat_local_state) 265 { 266 return ((plat_local_state > PLAT_MAX_RET_STATE) && 267 (plat_local_state <= PLAT_MAX_OFF_STATE)) ? 1 : 0; 268 } 269 270 /***************************************************************************** 271 * This data structure defines the representation of the power state parameter 272 * for its exchange between the generic PSCI code and the platform port. For 273 * example, it is used by the platform port to specify the requested power 274 * states during a power management operation. It is used by the generic code to 275 * inform the platform about the target power states that each level should 276 * enter. 277 ****************************************************************************/ 278 typedef struct psci_power_state { 279 /* 280 * The pwr_domain_state[] stores the local power state at each level 281 * for the CPU. 282 */ 283 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 284 #if PSCI_OS_INIT_MODE 285 /* 286 * The highest power level at which the current CPU is the last running 287 * CPU. 288 */ 289 unsigned int last_at_pwrlvl; 290 #endif 291 } psci_power_state_t; 292 293 /******************************************************************************* 294 * Structure used to store per-cpu information relevant to the PSCI service. 295 * It is populated in the per-cpu data array. In return we get a guarantee that 296 * this information will not reside on a cache line shared with another cpu. 297 ******************************************************************************/ 298 typedef struct psci_cpu_data { 299 /* State as seen by PSCI Affinity Info API */ 300 aff_info_state_t aff_info_state; 301 302 /* 303 * Highest power level which takes part in a power management 304 * operation. 305 */ 306 unsigned int target_pwrlvl; 307 308 /* The local power state of this CPU */ 309 plat_local_state_t local_state; 310 } psci_cpu_data_t; 311 312 /******************************************************************************* 313 * Structure populated by platform specific code to export routines which 314 * perform common low level power management functions 315 ******************************************************************************/ 316 typedef struct plat_psci_ops { 317 void (*cpu_standby)(plat_local_state_t cpu_state); 318 int (*pwr_domain_on)(u_register_t mpidr); 319 void (*pwr_domain_off)(const psci_power_state_t *target_state); 320 void (*pwr_domain_suspend_pwrdown_early)( 321 const psci_power_state_t *target_state); 322 #if PSCI_OS_INIT_MODE 323 int (*pwr_domain_suspend)(const psci_power_state_t *target_state); 324 #else 325 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 326 #endif 327 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 328 void (*pwr_domain_on_finish_late)( 329 const psci_power_state_t *target_state); 330 void (*pwr_domain_suspend_finish)( 331 const psci_power_state_t *target_state); 332 void __dead2 (*pwr_domain_pwr_down_wfi)( 333 const psci_power_state_t *target_state); 334 void __dead2 (*system_off)(void); 335 void __dead2 (*system_reset)(void); 336 int (*validate_power_state)(unsigned int power_state, 337 psci_power_state_t *req_state); 338 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 339 void (*get_sys_suspend_power_state)( 340 psci_power_state_t *req_state); 341 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 342 int pwrlvl); 343 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 344 unsigned int power_state, 345 psci_power_state_t *output_state); 346 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 347 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 348 int (*read_mem_protect)(int *val); 349 int (*write_mem_protect)(int val); 350 int (*system_reset2)(int is_vendor, 351 int reset_type, u_register_t cookie); 352 } plat_psci_ops_t; 353 354 /******************************************************************************* 355 * Function & Data prototypes 356 ******************************************************************************/ 357 unsigned int psci_version(void); 358 int psci_cpu_on(u_register_t target_cpu, 359 uintptr_t entrypoint, 360 u_register_t context_id); 361 int psci_cpu_suspend(unsigned int power_state, 362 uintptr_t entrypoint, 363 u_register_t context_id); 364 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 365 int psci_cpu_off(void); 366 int psci_affinity_info(u_register_t target_affinity, 367 unsigned int lowest_affinity_level); 368 int psci_migrate(u_register_t target_cpu); 369 int psci_migrate_info_type(void); 370 u_register_t psci_migrate_info_up_cpu(void); 371 int psci_node_hw_state(u_register_t target_cpu, 372 unsigned int power_level); 373 int psci_features(unsigned int psci_fid); 374 #if PSCI_OS_INIT_MODE 375 int psci_set_suspend_mode(unsigned int mode); 376 #endif 377 void __dead2 psci_power_down_wfi(void); 378 void psci_arch_setup(void); 379 380 #endif /*__ASSEMBLER__*/ 381 382 #endif /* PSCI_H */ 383