1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PSCI_H__ 32 #define __PSCI_H__ 33 34 #include <bakery_lock.h> 35 #include <bl_common.h> 36 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 37 #if ENABLE_PLAT_COMPAT 38 #include <psci_compat.h> 39 #endif 40 41 /******************************************************************************* 42 * Number of power domains whose state this PSCI implementation can track 43 ******************************************************************************/ 44 #ifdef PLAT_NUM_PWR_DOMAINS 45 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 46 #else 47 #define PSCI_NUM_PWR_DOMAINS (2 * PLATFORM_CORE_COUNT) 48 #endif 49 50 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 51 PLATFORM_CORE_COUNT) 52 53 /* This is the power level corresponding to a CPU */ 54 #define PSCI_CPU_PWR_LVL 0 55 56 /* 57 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 58 * uses the old power_state parameter format which has 2 bits to specify the 59 * power level, this constant is defined to be 3. 60 */ 61 #define PSCI_MAX_PWR_LVL 3 62 63 /******************************************************************************* 64 * Defines for runtime services function ids 65 ******************************************************************************/ 66 #define PSCI_VERSION 0x84000000 67 #define PSCI_CPU_SUSPEND_AARCH32 0x84000001 68 #define PSCI_CPU_SUSPEND_AARCH64 0xc4000001 69 #define PSCI_CPU_OFF 0x84000002 70 #define PSCI_CPU_ON_AARCH32 0x84000003 71 #define PSCI_CPU_ON_AARCH64 0xc4000003 72 #define PSCI_AFFINITY_INFO_AARCH32 0x84000004 73 #define PSCI_AFFINITY_INFO_AARCH64 0xc4000004 74 #define PSCI_MIG_AARCH32 0x84000005 75 #define PSCI_MIG_AARCH64 0xc4000005 76 #define PSCI_MIG_INFO_TYPE 0x84000006 77 #define PSCI_MIG_INFO_UP_CPU_AARCH32 0x84000007 78 #define PSCI_MIG_INFO_UP_CPU_AARCH64 0xc4000007 79 #define PSCI_SYSTEM_OFF 0x84000008 80 #define PSCI_SYSTEM_RESET 0x84000009 81 #define PSCI_FEATURES 0x8400000A 82 #define PSCI_NODE_HW_STATE_AARCH32 0x8400000d 83 #define PSCI_NODE_HW_STATE_AARCH64 0xc400000d 84 #define PSCI_SYSTEM_SUSPEND_AARCH32 0x8400000E 85 #define PSCI_SYSTEM_SUSPEND_AARCH64 0xc400000E 86 #define PSCI_STAT_RESIDENCY_AARCH32 0x84000010 87 #define PSCI_STAT_RESIDENCY_AARCH64 0xc4000010 88 #define PSCI_STAT_COUNT_AARCH32 0x84000011 89 #define PSCI_STAT_COUNT_AARCH64 0xc4000011 90 91 /* Macro to help build the psci capabilities bitfield */ 92 #define define_psci_cap(x) (1 << (x & 0x1f)) 93 94 /* 95 * Number of PSCI calls (above) implemented 96 */ 97 #if ENABLE_PSCI_STAT 98 #define PSCI_NUM_CALLS 22 99 #else 100 #define PSCI_NUM_CALLS 18 101 #endif 102 103 /* The macros below are used to identify PSCI calls from the SMC function ID */ 104 #define PSCI_FID_MASK 0xffe0u 105 #define PSCI_FID_VALUE 0u 106 #define is_psci_fid(_fid) \ 107 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 108 109 /******************************************************************************* 110 * PSCI Migrate and friends 111 ******************************************************************************/ 112 #define PSCI_TOS_UP_MIG_CAP 0 113 #define PSCI_TOS_NOT_UP_MIG_CAP 1 114 #define PSCI_TOS_NOT_PRESENT_MP 2 115 116 /******************************************************************************* 117 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 118 ******************************************************************************/ 119 #define PSTATE_ID_SHIFT 0 120 121 #if PSCI_EXTENDED_STATE_ID 122 #define PSTATE_VALID_MASK 0xB0000000 123 #define PSTATE_TYPE_SHIFT 30 124 #define PSTATE_ID_MASK 0xfffffff 125 #else 126 #define PSTATE_VALID_MASK 0xFCFE0000 127 #define PSTATE_TYPE_SHIFT 16 128 #define PSTATE_PWR_LVL_SHIFT 24 129 #define PSTATE_ID_MASK 0xffff 130 #define PSTATE_PWR_LVL_MASK 0x3 131 132 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 133 PSTATE_PWR_LVL_MASK) 134 #define psci_make_powerstate(state_id, type, pwrlvl) \ 135 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 136 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 137 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 138 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 139 140 #define PSTATE_TYPE_STANDBY 0x0 141 #define PSTATE_TYPE_POWERDOWN 0x1 142 #define PSTATE_TYPE_MASK 0x1 143 144 #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ 145 PSTATE_ID_MASK) 146 #define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ 147 PSTATE_TYPE_MASK) 148 #define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) 149 150 /******************************************************************************* 151 * PSCI CPU_FEATURES feature flag specific defines 152 ******************************************************************************/ 153 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 154 #define FF_PSTATE_SHIFT 1 155 #define FF_PSTATE_ORIG 0 156 #define FF_PSTATE_EXTENDED 1 157 #if PSCI_EXTENDED_STATE_ID 158 #define FF_PSTATE FF_PSTATE_EXTENDED 159 #else 160 #define FF_PSTATE FF_PSTATE_ORIG 161 #endif 162 163 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 164 #define FF_MODE_SUPPORT_SHIFT 0 165 #define FF_SUPPORTS_OS_INIT_MODE 1 166 167 /******************************************************************************* 168 * PSCI version 169 ******************************************************************************/ 170 #define PSCI_MAJOR_VER (1 << 16) 171 #define PSCI_MINOR_VER 0x0 172 173 /******************************************************************************* 174 * PSCI error codes 175 ******************************************************************************/ 176 #define PSCI_E_SUCCESS 0 177 #define PSCI_E_NOT_SUPPORTED -1 178 #define PSCI_E_INVALID_PARAMS -2 179 #define PSCI_E_DENIED -3 180 #define PSCI_E_ALREADY_ON -4 181 #define PSCI_E_ON_PENDING -5 182 #define PSCI_E_INTERN_FAIL -6 183 #define PSCI_E_NOT_PRESENT -7 184 #define PSCI_E_DISABLED -8 185 #define PSCI_E_INVALID_ADDRESS -9 186 187 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 188 189 #ifndef __ASSEMBLY__ 190 191 #include <stdint.h> 192 #include <types.h> 193 194 /* 195 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 196 * CPU. The definitions of these states can be found in Section 5.7.1 in the 197 * PSCI specification (ARM DEN 0022C). 198 */ 199 typedef enum { 200 AFF_STATE_ON = 0, 201 AFF_STATE_OFF = 1, 202 AFF_STATE_ON_PENDING = 2 203 } aff_info_state_t; 204 205 /* 206 * These are the power states reported by PSCI_NODE_HW_STATE API for the 207 * specified CPU. The definitions of these states can be found in Section 5.15.3 208 * of PSCI specification (ARM DEN 0022C). 209 */ 210 typedef enum { 211 HW_ON = 0, 212 HW_OFF = 1, 213 HW_STANDBY = 2 214 } node_hw_state_t; 215 216 /* 217 * Macro to represent invalid affinity level within PSCI. 218 */ 219 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + 1) 220 221 /* 222 * Type for representing the local power state at a particular level. 223 */ 224 typedef uint8_t plat_local_state_t; 225 226 /* The local state macro used to represent RUN state. */ 227 #define PSCI_LOCAL_STATE_RUN 0 228 229 /* 230 * Macro to test whether the plat_local_state is RUN state 231 */ 232 #define is_local_state_run(plat_local_state) \ 233 ((plat_local_state) == PSCI_LOCAL_STATE_RUN) 234 235 /* 236 * Macro to test whether the plat_local_state is RETENTION state 237 */ 238 #define is_local_state_retn(plat_local_state) \ 239 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ 240 ((plat_local_state) <= PLAT_MAX_RET_STATE)) 241 242 /* 243 * Macro to test whether the plat_local_state is OFF state 244 */ 245 #define is_local_state_off(plat_local_state) \ 246 (((plat_local_state) > PLAT_MAX_RET_STATE) && \ 247 ((plat_local_state) <= PLAT_MAX_OFF_STATE)) 248 249 /***************************************************************************** 250 * This data structure defines the representation of the power state parameter 251 * for its exchange between the generic PSCI code and the platform port. For 252 * example, it is used by the platform port to specify the requested power 253 * states during a power management operation. It is used by the generic code to 254 * inform the platform about the target power states that each level should 255 * enter. 256 ****************************************************************************/ 257 typedef struct psci_power_state { 258 /* 259 * The pwr_domain_state[] stores the local power state at each level 260 * for the CPU. 261 */ 262 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + 1]; 263 } psci_power_state_t; 264 265 /******************************************************************************* 266 * Structure used to store per-cpu information relevant to the PSCI service. 267 * It is populated in the per-cpu data array. In return we get a guarantee that 268 * this information will not reside on a cache line shared with another cpu. 269 ******************************************************************************/ 270 typedef struct psci_cpu_data { 271 /* State as seen by PSCI Affinity Info API */ 272 aff_info_state_t aff_info_state; 273 274 /* 275 * Highest power level which takes part in a power management 276 * operation. 277 */ 278 unsigned char target_pwrlvl; 279 280 /* The local power state of this CPU */ 281 plat_local_state_t local_state; 282 } psci_cpu_data_t; 283 284 /******************************************************************************* 285 * Structure populated by platform specific code to export routines which 286 * perform common low level power management functions 287 ******************************************************************************/ 288 typedef struct plat_psci_ops { 289 void (*cpu_standby)(plat_local_state_t cpu_state); 290 int (*pwr_domain_on)(u_register_t mpidr); 291 void (*pwr_domain_off)(const psci_power_state_t *target_state); 292 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 293 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 294 void (*pwr_domain_suspend_finish)( 295 const psci_power_state_t *target_state); 296 void (*pwr_domain_pwr_down_wfi)( 297 const psci_power_state_t *target_state) __dead2; 298 void (*system_off)(void) __dead2; 299 void (*system_reset)(void) __dead2; 300 int (*validate_power_state)(unsigned int power_state, 301 psci_power_state_t *req_state); 302 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 303 void (*get_sys_suspend_power_state)( 304 psci_power_state_t *req_state); 305 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 306 int pwrlvl); 307 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 308 unsigned int power_state, 309 psci_power_state_t *output_state); 310 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 311 } plat_psci_ops_t; 312 313 /******************************************************************************* 314 * Optional structure populated by the Secure Payload Dispatcher to be given a 315 * chance to perform any bookkeeping before PSCI executes a power management 316 * operation. It also allows PSCI to determine certain properties of the SP e.g. 317 * migrate capability etc. 318 ******************************************************************************/ 319 typedef struct spd_pm_ops { 320 void (*svc_on)(u_register_t target_cpu); 321 int32_t (*svc_off)(u_register_t __unused); 322 void (*svc_suspend)(u_register_t max_off_pwrlvl); 323 void (*svc_on_finish)(u_register_t __unused); 324 void (*svc_suspend_finish)(u_register_t max_off_pwrlvl); 325 int32_t (*svc_migrate)(u_register_t from_cpu, u_register_t to_cpu); 326 int32_t (*svc_migrate_info)(u_register_t *resident_cpu); 327 void (*svc_system_off)(void); 328 void (*svc_system_reset)(void); 329 } spd_pm_ops_t; 330 331 /******************************************************************************* 332 * Function & Data prototypes 333 ******************************************************************************/ 334 unsigned int psci_version(void); 335 int psci_cpu_on(u_register_t target_cpu, 336 uintptr_t entrypoint, 337 u_register_t context_id); 338 int psci_cpu_suspend(unsigned int power_state, 339 uintptr_t entrypoint, 340 u_register_t context_id); 341 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 342 int psci_cpu_off(void); 343 int psci_affinity_info(u_register_t target_affinity, 344 unsigned int lowest_affinity_level); 345 int psci_migrate(u_register_t target_cpu); 346 int psci_migrate_info_type(void); 347 long psci_migrate_info_up_cpu(void); 348 int psci_node_hw_state(u_register_t target_cpu, 349 unsigned int power_level); 350 int psci_features(unsigned int psci_fid); 351 void __dead2 psci_power_down_wfi(void); 352 void psci_arch_setup(void); 353 354 /* 355 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 356 * AArch64. 357 */ 358 void psci_entrypoint(void) __deprecated; 359 360 /* 361 * Function prototype for the warmboot entrypoint function which will be 362 * programmed in the mailbox by the platform. 363 */ 364 typedef void (*mailbox_entrypoint_t)(void); 365 366 /****************************************************************************** 367 * Structure to pass PSCI Library arguments. 368 *****************************************************************************/ 369 typedef struct psci_lib_args { 370 /* The version information of PSCI Library Interface */ 371 param_header_t h; 372 /* The warm boot entrypoint function */ 373 mailbox_entrypoint_t mailbox_ep; 374 } psci_lib_args_t; 375 376 /* Helper macro to set the psci_lib_args_t structure at runtime */ 377 #define SET_PSCI_LIB_ARGS_V1(_p, _entry) do { \ 378 SET_PARAM_HEAD(_p, PARAM_PSCI_LIB_ARGS, VERSION_1, 0); \ 379 (_p)->mailbox_ep = (_entry); \ 380 } while (0) 381 382 /* Helper macro to define the psci_lib_args_t statically */ 383 #define DEFINE_STATIC_PSCI_LIB_ARGS_V1(_name, _entry) \ 384 static const psci_lib_args_t (_name) = { \ 385 .h.type = (uint8_t)PARAM_PSCI_LIB_ARGS, \ 386 .h.version = (uint8_t)VERSION_1, \ 387 .h.size = (uint16_t)sizeof(_name), \ 388 .h.attr = 0, \ 389 .mailbox_ep = (_entry) \ 390 } 391 392 /* Helper macro to verify the pointer to psci_lib_args_t structure */ 393 #define VERIFY_PSCI_LIB_ARGS_V1(_p) ((_p) \ 394 && ((_p)->h.type == PARAM_PSCI_LIB_ARGS) \ 395 && ((_p)->h.version == VERSION_1) \ 396 && ((_p)->h.size == sizeof(*(_p))) \ 397 && ((_p)->h.attr == 0) \ 398 && ((_p)->mailbox_ep)) 399 400 /****************************************************************************** 401 * PSCI Library Interfaces 402 *****************************************************************************/ 403 u_register_t psci_smc_handler(uint32_t smc_fid, 404 u_register_t x1, 405 u_register_t x2, 406 u_register_t x3, 407 u_register_t x4, 408 void *cookie, 409 void *handle, 410 u_register_t flags); 411 int psci_setup(const psci_lib_args_t *lib_args); 412 void psci_warmboot_entrypoint(void); 413 void psci_register_spd_pm_hook(const spd_pm_ops_t *pm); 414 void psci_prepare_next_non_secure_ctx( 415 entry_point_info_t *next_image_info); 416 417 #endif /*__ASSEMBLY__*/ 418 419 #endif /* __PSCI_H__ */ 420