1 /* 2 * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CPU_DATA_H 8 #define CPU_DATA_H 9 10 #include <platform_def.h> /* CACHE_WRITEBACK_GRANULE required */ 11 12 #include <bl31/ehf.h> 13 #include <context.h> 14 #include <lib/utils_def.h> 15 #include <lib/cpus/cpu_ops.h> 16 17 /* need enough space in crash buffer to save 8 registers */ 18 #define CPU_DATA_CRASH_BUF_BYTES 64 19 #if ENABLE_RUNTIME_INSTRUMENTATION 20 /* Temporary space to store PMF timestamps from assembly code */ 21 #define CPU_DATA_PMF_TS_COUNT 1 22 #define CPU_DATA_PMF_TS0_IDX 0 23 #endif 24 25 #ifdef __aarch64__ 26 #define CPU_DATA_CPU_CONTEXT_SIZE (CPU_CONTEXT_NUM * CPU_WORD_SIZE) 27 #else /* __aarch64__ */ 28 #define CPU_DATA_CPU_CONTEXT_SIZE 0 29 #endif /* __aarch64__ */ 30 #define CPU_DATA_WARMBOOT_EP_INFO_SIZE CPU_WORD_SIZE 31 #define CPU_DATA_WARMBOOT_EP_INFO_ALIGN CPU_WORD_SIZE 32 #define CPU_DATA_CPU_OPS_PTR_SIZE CPU_WORD_SIZE 33 #define CPU_DATA_CPU_OPS_PTR_ALIGN CPU_WORD_SIZE 34 #define CPU_DATA_PSCI_SVC_CPU_DATA_SIZE 12 35 #define CPU_DATA_PSCI_SVC_CPU_DATA_ALIGN CPU_WORD_SIZE 36 #if ENABLE_PAUTH 37 /* uint64_t apiakey[2] */ 38 #define CPU_DATA_APIAKEY_SIZE 16 39 /* uint64_t alignement */ 40 #define CPU_DATA_APIAKEY_ALIGN 8 41 #else /* ENABLE_PAUTH */ 42 #define CPU_DATA_APIAKEY_SIZE 0 43 #define CPU_DATA_APIAKEY_ALIGN 1 44 #endif /* ENABLE_PAUTH */ 45 #if CRASH_REPORTING 46 #define CPU_DATA_CRASH_BUF_SIZE ((CPU_DATA_CRASH_BUF_BYTES >> 3) * CPU_WORD_SIZE) 47 #define CPU_DATA_CRASH_BUF_ALIGN CPU_WORD_SIZE 48 #else /* CRASH_REPORTING */ 49 #define CPU_DATA_CRASH_BUF_SIZE 0 50 #define CPU_DATA_CRASH_BUF_ALIGN 1 51 #endif /* CRASH_REPORTING */ 52 #if ENABLE_RUNTIME_INSTRUMENTATION 53 #define CPU_DATA_CPU_DATA_PMF_TS_SIZE (CPU_DATA_PMF_TS_COUNT * 8) 54 /* uint64_t alignement */ 55 #define CPU_DATA_CPU_DATA_PMF_TS_ALIGN 8 56 #else /* ENABLE_RUNTIME_INSTRUMENTATION */ 57 #define CPU_DATA_CPU_DATA_PMF_TS_SIZE 0 58 #define CPU_DATA_CPU_DATA_PMF_TS_ALIGN 1 59 #endif /* ENABLE_RUNTIME_INSTRUMENTATION */ 60 #ifdef PLAT_PCPU_DATA_SIZE 61 #define CPU_DATA_PLATFORM_CPU_DATA_SIZE PLAT_PCPU_DATA_SIZE 62 #define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1 63 #else /* PLAT_PCPU_DATA_SIZE */ 64 #define CPU_DATA_PLATFORM_CPU_DATA_SIZE 0 65 #define CPU_DATA_PLATFORM_CPU_DATA_ALIGN 1 66 #endif /* PLAT_PCPU_DATA_SIZE */ 67 #if EL3_EXCEPTION_HANDLING 68 /* buffer space for EHF data is sizeof(pe_exc_data_t) */ 69 #define CPU_DATA_EHF_DATA_SIZE 8 70 /* hardcoded to 64 bit alignment */ 71 #define CPU_DATA_EHF_DATA_ALIGN 8 72 #else /* EL3_EXCEPTION_HANDLING */ 73 #define CPU_DATA_EHF_DATA_SIZE 0 74 #define CPU_DATA_EHF_DATA_ALIGN 1 75 #endif 76 /* cpu_data size is the data size rounded up to the platform cache line size */ 77 #define CPU_DATA_SIZE_ALIGN CACHE_WRITEBACK_GRANULE 78 79 #define CPU_DATA_CPU_CONTEXT 0 80 #define CPU_DATA_WARMBOOT_EP_INFO ROUND_UP_2EVAL((CPU_DATA_CPU_CONTEXT + CPU_DATA_CPU_CONTEXT_SIZE), CPU_DATA_CPU_OPS_PTR_ALIGN) 81 #define CPU_DATA_CPU_OPS_PTR ROUND_UP_2EVAL((CPU_DATA_WARMBOOT_EP_INFO + CPU_DATA_WARMBOOT_EP_INFO_SIZE), CPU_DATA_CPU_OPS_PTR_ALIGN) 82 #define CPU_DATA_PSCI_SVC_CPU_DATA ROUND_UP_2EVAL((CPU_DATA_CPU_OPS_PTR + CPU_DATA_CPU_OPS_PTR_SIZE), CPU_DATA_PSCI_SVC_CPU_DATA_ALIGN) 83 #define CPU_DATA_APIAKEY ROUND_UP_2EVAL((CPU_DATA_PSCI_SVC_CPU_DATA + CPU_DATA_PSCI_SVC_CPU_DATA_SIZE), CPU_DATA_APIAKEY_ALIGN) 84 #define CPU_DATA_CRASH_BUF ROUND_UP_2EVAL((CPU_DATA_APIAKEY + CPU_DATA_APIAKEY_SIZE), CPU_DATA_CRASH_BUF_ALIGN) 85 #define CPU_DATA_CPU_DATA_PMF_TS ROUND_UP_2EVAL((CPU_DATA_CRASH_BUF + CPU_DATA_CRASH_BUF_SIZE), CPU_DATA_CPU_DATA_PMF_TS_ALIGN) 86 #define CPU_DATA_PLATFORM_CPU_DATA ROUND_UP_2EVAL((CPU_DATA_CPU_DATA_PMF_TS + CPU_DATA_CPU_DATA_PMF_TS_SIZE), CPU_DATA_PLATFORM_CPU_DATA_ALIGN) 87 #define CPU_DATA_EHF_DATA ROUND_UP_2EVAL((CPU_DATA_PLATFORM_CPU_DATA + CPU_DATA_PLATFORM_CPU_DATA_SIZE), CPU_DATA_EHF_DATA_ALIGN) 88 #define CPU_DATA_SIZE ROUND_UP_2EVAL((CPU_DATA_EHF_DATA + CPU_DATA_EHF_DATA_SIZE), CPU_DATA_SIZE_ALIGN) 89 90 #ifndef __ASSEMBLER__ 91 92 #include <assert.h> 93 #include <stdint.h> 94 95 #include <arch_helpers.h> 96 #include <lib/cassert.h> 97 #include <lib/per_cpu/per_cpu.h> 98 #include <lib/psci/psci.h> 99 100 #include <platform_def.h> 101 102 /******************************************************************************* 103 * Function & variable prototypes 104 ******************************************************************************/ 105 106 /******************************************************************************* 107 * Cache of frequently used per-cpu data: 108 * Pointers to non-secure, realm, and secure security state contexts 109 * Address of the crash stack 110 * It is aligned to the cache line boundary to allow efficient concurrent 111 * manipulation of these pointers on different cpus 112 * 113 * The data structure and the _cpu_data accessors should not be used directly 114 * by components that have per-cpu members. The member access macros should be 115 * used for this. 116 ******************************************************************************/ 117 typedef struct cpu_data { 118 #ifdef __aarch64__ 119 void *cpu_context[CPU_CONTEXT_NUM]; 120 #endif /* __aarch64__ */ 121 entry_point_info_t *warmboot_ep_info; 122 struct cpu_ops *cpu_ops_ptr; 123 struct psci_cpu_data psci_svc_cpu_data; 124 #if ENABLE_PAUTH 125 uint64_t apiakey[2]; 126 #endif 127 #if CRASH_REPORTING 128 u_register_t crash_buf[CPU_DATA_CRASH_BUF_BYTES >> 3]; 129 #endif 130 #if ENABLE_RUNTIME_INSTRUMENTATION 131 uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT]; 132 #endif 133 #if PLAT_PCPU_DATA_SIZE 134 uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; 135 #endif 136 #if EL3_EXCEPTION_HANDLING 137 pe_exc_data_t ehf_data; 138 #endif 139 } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; 140 141 PER_CPU_DECLARE(cpu_data_t, percpu_data); 142 143 #define CPU_DATA_ASSERT_OFFSET(left, right) \ 144 CASSERT(CPU_DATA_ ## left == __builtin_offsetof \ 145 (cpu_data_t, right), \ 146 assert_cpu_data_ ## right ## _mismatch) 147 148 /* verify assembler offsets match data structures */ 149 CPU_DATA_ASSERT_OFFSET(WARMBOOT_EP_INFO, warmboot_ep_info); 150 CPU_DATA_ASSERT_OFFSET(CPU_OPS_PTR, cpu_ops_ptr); 151 CPU_DATA_ASSERT_OFFSET(PSCI_SVC_CPU_DATA, psci_svc_cpu_data); 152 #if ENABLE_PAUTH 153 CPU_DATA_ASSERT_OFFSET(APIAKEY, apiakey); 154 #endif 155 #if CRASH_REPORTING 156 CPU_DATA_ASSERT_OFFSET(CRASH_BUF, crash_buf); 157 #endif 158 #if ENABLE_RUNTIME_INSTRUMENTATION 159 CPU_DATA_ASSERT_OFFSET(CPU_DATA_PMF_TS, cpu_data_pmf_ts); 160 #endif 161 #if PLAT_PCPU_DATA_SIZE 162 CPU_DATA_ASSERT_OFFSET(PLATFORM_CPU_DATA, platform_cpu_data); 163 #endif 164 #if EL3_EXCEPTION_HANDLING 165 CPU_DATA_ASSERT_OFFSET(EHF_DATA, ehf_data); 166 #endif 167 168 CASSERT(CPU_DATA_SIZE == sizeof(cpu_data_t), 169 assert_cpu_data_size_mismatch); 170 171 #ifndef __aarch64__ 172 cpu_data_t *_cpu_data(void); 173 #endif 174 175 /************************************************************************** 176 * APIs for initialising and accessing per-cpu data 177 *************************************************************************/ 178 179 void cpu_data_init_cpu_ops(void); 180 181 #define get_cpu_data(_m) PER_CPU_CUR(percpu_data)->_m 182 #define set_cpu_data(_m, _v) PER_CPU_CUR(percpu_data)->_m = (_v) 183 #define get_cpu_data_by_index(_ix, _m) PER_CPU_BY_INDEX(percpu_data, _ix)->_m 184 #define set_cpu_data_by_index(_ix, _m, _v) PER_CPU_BY_INDEX(percpu_data, _ix)->_m = (_v) 185 /* ((cpu_data_t *)0)->_m is a dummy to get the sizeof the struct member _m */ 186 #define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \ 187 &(PER_CPU_CUR(percpu_data)->_m), \ 188 sizeof(((cpu_data_t *)0)->_m)) 189 #define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \ 190 &(PER_CPU_CUR(percpu_data)->_m), \ 191 sizeof(((cpu_data_t *)0)->_m)) 192 #define flush_cpu_data_by_index(_ix, _m) \ 193 flush_dcache_range((uintptr_t) \ 194 &(PER_CPU_BY_INDEX(percpu_data, _ix)->_m), \ 195 sizeof(((cpu_data_t *)0)->_m)) 196 197 198 #endif /* __ASSEMBLER__ */ 199 #endif /* CPU_DATA_H */ 200