1 /* 2 * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_EL1_H 8 #define CONTEXT_EL1_H 9 10 #include <lib/extensions/sysreg128.h> 11 12 #ifndef __ASSEMBLER__ 13 14 /******************************************************************************* 15 * EL1 Registers: 16 * AArch64 EL1 system register context structure for preserving the 17 * architectural state during world switches. 18 ******************************************************************************/ 19 20 typedef struct el1_common_regs { 21 uint64_t spsr_el1; 22 uint64_t elr_el1; 23 24 #if (!ERRATA_SPECULATIVE_AT) 25 uint64_t sctlr_el1; 26 uint64_t tcr_el1; 27 #endif /* ERRATA_SPECULATIVE_AT=0 */ 28 29 uint64_t cpacr_el1; 30 uint64_t csselr_el1; 31 uint64_t sp_el1; 32 uint64_t esr_el1; 33 uint64_t mair_el1; 34 uint64_t amair_el1; 35 uint64_t actlr_el1; 36 uint64_t tpidr_el1; 37 uint64_t tpidr_el0; 38 uint64_t tpidrro_el0; 39 uint64_t far_el1; 40 uint64_t afsr0_el1; 41 uint64_t afsr1_el1; 42 uint64_t contextidr_el1; 43 uint64_t vbar_el1; 44 uint64_t mdccint_el1; 45 uint64_t mdscr_el1; 46 sysreg_t par_el1; 47 sysreg_t ttbr0_el1; 48 sysreg_t ttbr1_el1; 49 } el1_common_regs_t; 50 51 typedef struct el1_aarch32_regs { 52 uint64_t spsr_abt; 53 uint64_t spsr_und; 54 uint64_t spsr_irq; 55 uint64_t spsr_fiq; 56 uint64_t dacr32_el2; 57 uint64_t ifsr32_el2; 58 } el1_aarch32_regs_t; 59 60 typedef struct el1_arch_timer_regs { 61 uint64_t cntp_ctl_el0; 62 uint64_t cntp_cval_el0; 63 uint64_t cntv_ctl_el0; 64 uint64_t cntv_cval_el0; 65 uint64_t cntkctl_el1; 66 } el1_arch_timer_regs_t; 67 68 typedef struct el1_mte2_regs { 69 uint64_t tfsre0_el1; 70 uint64_t tfsr_el1; 71 uint64_t rgsr_el1; 72 uint64_t gcr_el1; 73 } el1_mte2_regs_t; 74 75 typedef struct el1_ras_regs { 76 uint64_t disr_el1; 77 } el1_ras_regs_t; 78 79 typedef struct el1_s1pie_regs { 80 uint64_t pire0_el1; 81 uint64_t pir_el1; 82 } el1_s1pie_regs_t; 83 84 typedef struct el1_s1poe_regs { 85 uint64_t por_el1; 86 } el1_s1poe_regs_t; 87 88 typedef struct el1_s2poe_regs { 89 uint64_t s2por_el1; 90 } el1_s2poe_regs_t; 91 92 typedef struct el1_tcr2_regs { 93 uint64_t tcr2_el1; 94 } el1_tcr2_regs_t; 95 96 typedef struct el1_trf_regs { 97 uint64_t trfcr_el1; 98 } el1_trf_regs_t; 99 100 typedef struct el1_csv2_2_regs { 101 uint64_t scxtnum_el0; 102 uint64_t scxtnum_el1; 103 } el1_csv2_2_regs_t; 104 105 typedef struct el1_gcs_regs { 106 uint64_t gcscr_el1; 107 uint64_t gcscre0_el1; 108 uint64_t gcspr_el1; 109 uint64_t gcspr_el0; 110 } el1_gcs_regs_t; 111 112 typedef struct el1_the_regs { 113 sysreg_t rcwmask_el1; 114 sysreg_t rcwsmask_el1; 115 } el1_the_regs_t; 116 117 typedef struct el1_sctlr2_regs { 118 uint64_t sctlr2_el1; 119 } el1_sctlr2_regs_t; 120 121 typedef struct el1_ls64_regs { 122 uint64_t accdata_el1; 123 } el1_ls64_regs_t; 124 125 typedef struct el1_sysregs { 126 127 el1_common_regs_t common; 128 129 #if CTX_INCLUDE_AARCH32_REGS 130 el1_aarch32_regs_t el1_aarch32; 131 #endif 132 133 #if NS_TIMER_SWITCH 134 el1_arch_timer_regs_t arch_timer; 135 #endif 136 137 #if ENABLE_FEAT_MTE2 138 el1_mte2_regs_t mte2; 139 #endif 140 141 #if ENABLE_FEAT_RAS 142 el1_ras_regs_t ras; 143 #endif 144 145 #if ENABLE_FEAT_S1PIE 146 el1_s1pie_regs_t s1pie; 147 #endif 148 149 #if ENABLE_FEAT_S1POE 150 el1_s1poe_regs_t s1poe; 151 #endif 152 153 #if ENABLE_FEAT_S2POE 154 el1_s2poe_regs_t s2poe; 155 #endif 156 157 #if ENABLE_FEAT_TCR2 158 el1_tcr2_regs_t tcr2; 159 #endif 160 161 #if ENABLE_TRF_FOR_NS 162 el1_trf_regs_t trf; 163 #endif 164 165 #if ENABLE_FEAT_CSV2_2 166 el1_csv2_2_regs_t csv2_2; 167 #endif 168 169 #if ENABLE_FEAT_GCS 170 el1_gcs_regs_t gcs; 171 #endif 172 173 #if ENABLE_FEAT_THE 174 el1_the_regs_t the; 175 #endif 176 177 #if ENABLE_FEAT_SCTLR2 178 el1_sctlr2_regs_t sctlr2; 179 #endif 180 181 #if ENABLE_FEAT_LS64_ACCDATA 182 el1_ls64_regs_t ls64; 183 #endif 184 } el1_sysregs_t; 185 186 187 /* 188 * Macros to access members related to individual features of the el1_sysregs_t 189 * structures. 190 */ 191 192 #define read_el1_ctx_common(ctx, reg) (((ctx)->common).reg) 193 194 #define write_el1_ctx_common(ctx, reg, val) ((((ctx)->common).reg) \ 195 = (uint64_t) (val)) 196 197 #define write_el1_ctx_common_sysreg128(ctx, reg, val) ((((ctx)->common).reg) \ 198 = (sysreg_t) (val)) 199 200 #if NS_TIMER_SWITCH 201 #define read_el1_ctx_arch_timer(ctx, reg) (((ctx)->arch_timer).reg) 202 #define write_el1_ctx_arch_timer(ctx, reg, val) ((((ctx)->arch_timer).reg) \ 203 = (uint64_t) (val)) 204 #else 205 #define read_el1_ctx_arch_timer(ctx, reg) ULL(0) 206 #define write_el1_ctx_arch_timer(ctx, reg, val) 207 #endif /* NS_TIMER_SWITCH */ 208 209 #if CTX_INCLUDE_AARCH32_REGS 210 #define read_el1_ctx_aarch32(ctx, reg) (((ctx)->el1_aarch32).reg) 211 #define write_el1_ctx_aarch32(ctx, reg, val) ((((ctx)->el1_aarch32).reg) \ 212 = (uint64_t) (val)) 213 #else 214 #define read_el1_ctx_aarch32(ctx, reg) ULL(0) 215 #define write_el1_ctx_aarch32(ctx, reg, val) 216 #endif /* CTX_INCLUDE_AARCH32_REGS */ 217 218 #if ENABLE_FEAT_MTE2 219 #define read_el1_ctx_mte2(ctx, reg) (((ctx)->mte2).reg) 220 #define write_el1_ctx_mte2(ctx, reg, val) ((((ctx)->mte2).reg) \ 221 = (uint64_t) (val)) 222 #else 223 #define read_el1_ctx_mte2(ctx, reg) ULL(0) 224 #define write_el1_ctx_mte2(ctx, reg, val) 225 #endif /* ENABLE_FEAT_MTE2 */ 226 227 #if ENABLE_FEAT_RAS 228 #define read_el1_ctx_ras(ctx, reg) (((ctx)->ras).reg) 229 #define write_el1_ctx_ras(ctx, reg, val) ((((ctx)->ras).reg) \ 230 = (uint64_t) (val)) 231 #else 232 #define read_el1_ctx_ras(ctx, reg) ULL(0) 233 #define write_el1_ctx_ras(ctx, reg, val) 234 #endif /* ENABLE_FEAT_RAS */ 235 236 #if ENABLE_FEAT_S1PIE 237 #define read_el1_ctx_s1pie(ctx, reg) (((ctx)->s1pie).reg) 238 #define write_el1_ctx_s1pie(ctx, reg, val) ((((ctx)->s1pie).reg) \ 239 = (uint64_t) (val)) 240 #else 241 #define read_el1_ctx_s1pie(ctx, reg) ULL(0) 242 #define write_el1_ctx_s1pie(ctx, reg, val) 243 #endif /* ENABLE_FEAT_S1PIE */ 244 245 #if ENABLE_FEAT_S1POE 246 #define read_el1_ctx_s1poe(ctx, reg) (((ctx)->s1poe).reg) 247 #define write_el1_ctx_s1poe(ctx, reg, val) ((((ctx)->s1poe).reg) \ 248 = (uint64_t) (val)) 249 #else 250 #define read_el1_ctx_s1poe(ctx, reg) ULL(0) 251 #define write_el1_ctx_s1poe(ctx, reg, val) 252 #endif /* ENABLE_FEAT_S1POE */ 253 254 #if ENABLE_FEAT_S2POE 255 #define read_el1_ctx_s2poe(ctx, reg) (((ctx)->s2poe).reg) 256 #define write_el1_ctx_s2poe(ctx, reg, val) ((((ctx)->s2poe).reg) \ 257 = (uint64_t) (val)) 258 #else 259 #define read_el1_ctx_s2poe(ctx, reg) ULL(0) 260 #define write_el1_ctx_s2poe(ctx, reg, val) 261 #endif /* ENABLE_FEAT_S2POE */ 262 263 #if ENABLE_FEAT_TCR2 264 #define read_el1_ctx_tcr2(ctx, reg) (((ctx)->tcr2).reg) 265 #define write_el1_ctx_tcr2(ctx, reg, val) ((((ctx)->tcr2).reg) \ 266 = (uint64_t) (val)) 267 #else 268 #define read_el1_ctx_tcr2(ctx, reg) ULL(0) 269 #define write_el1_ctx_tcr2(ctx, reg, val) 270 #endif /* ENABLE_FEAT_TCR2 */ 271 272 #if ENABLE_TRF_FOR_NS 273 #define read_el1_ctx_trf(ctx, reg) (((ctx)->trf).reg) 274 #define write_el1_ctx_trf(ctx, reg, val) ((((ctx)->trf).reg) \ 275 = (uint64_t) (val)) 276 #else 277 #define read_el1_ctx_trf(ctx, reg) ULL(0) 278 #define write_el1_ctx_trf(ctx, reg, val) 279 #endif /* ENABLE_TRF_FOR_NS */ 280 281 #if ENABLE_FEAT_CSV2_2 282 #define read_el1_ctx_csv2_2(ctx, reg) (((ctx)->csv2_2).reg) 283 #define write_el1_ctx_csv2_2(ctx, reg, val) ((((ctx)->csv2_2).reg) \ 284 = (uint64_t) (val)) 285 #else 286 #define read_el1_ctx_csv2_2(ctx, reg) ULL(0) 287 #define write_el1_ctx_csv2_2(ctx, reg, val) 288 #endif /* ENABLE_FEAT_CSV2_2 */ 289 290 #if ENABLE_FEAT_GCS 291 #define read_el1_ctx_gcs(ctx, reg) (((ctx)->gcs).reg) 292 #define write_el1_ctx_gcs(ctx, reg, val) ((((ctx)->gcs).reg) \ 293 = (uint64_t) (val)) 294 #else 295 #define read_el1_ctx_gcs(ctx, reg) ULL(0) 296 #define write_el1_ctx_gcs(ctx, reg, val) 297 #endif /* ENABLE_FEAT_GCS */ 298 299 #if ENABLE_FEAT_THE 300 #define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg) 301 #define write_el1_ctx_the_sysreg128(ctx, reg, val) ((((ctx)->the).reg) \ 302 = (sysreg_t) (val)) 303 #else 304 #define read_el1_ctx_the(ctx, reg) ULL(0) 305 #define write_el1_ctx_the_sysreg128(ctx, reg, val) 306 #endif /* ENABLE_FEAT_THE */ 307 308 #if ENABLE_FEAT_SCTLR2 309 #define read_el1_ctx_sctlr2(ctx, reg) (((ctx)->sctlr2).reg) 310 #define write_el1_ctx_sctlr2(ctx, reg, val) ((((ctx)->sctlr2).reg) \ 311 = (uint64_t) (val)) 312 #else 313 #define read_el1_ctx_sctlr2(ctx, reg) ULL(0) 314 #define write_el1_ctx_sctlr2(ctx, reg, val) 315 #endif /* ENABLE_FEAT_SCTLR2 */ 316 317 #if ENABLE_FEAT_LS64_ACCDATA 318 #define read_el1_ctx_ls64(ctx, reg) (((ctx)->ls64).reg) 319 #define write_el1_ctx_ls64(ctx, reg, val) ((((ctx)->ls64).reg) \ 320 = (uint64_t) (val)) 321 #else 322 #define read_el1_ctx_ls64(ctx, reg) ULL(0) 323 #define write_el1_ctx_ls64(ctx, reg, val) 324 #endif /* ENABLE_FEAT_LS64_ACCDATA */ 325 /******************************************************************************/ 326 #endif /* __ASSEMBLER__ */ 327 328 #endif /* CONTEXT_EL1_H */ 329