1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CONTEXT_H__ 8 #define __CONTEXT_H__ 9 10 /******************************************************************************* 11 * Constants that allow assembler code to access members of and the 'gp_regs' 12 * structure at their correct offsets. 13 ******************************************************************************/ 14 #define CTX_GPREGS_OFFSET U(0x0) 15 #define CTX_GPREG_X0 U(0x0) 16 #define CTX_GPREG_X1 U(0x8) 17 #define CTX_GPREG_X2 U(0x10) 18 #define CTX_GPREG_X3 U(0x18) 19 #define CTX_GPREG_X4 U(0x20) 20 #define CTX_GPREG_X5 U(0x28) 21 #define CTX_GPREG_X6 U(0x30) 22 #define CTX_GPREG_X7 U(0x38) 23 #define CTX_GPREG_X8 U(0x40) 24 #define CTX_GPREG_X9 U(0x48) 25 #define CTX_GPREG_X10 U(0x50) 26 #define CTX_GPREG_X11 U(0x58) 27 #define CTX_GPREG_X12 U(0x60) 28 #define CTX_GPREG_X13 U(0x68) 29 #define CTX_GPREG_X14 U(0x70) 30 #define CTX_GPREG_X15 U(0x78) 31 #define CTX_GPREG_X16 U(0x80) 32 #define CTX_GPREG_X17 U(0x88) 33 #define CTX_GPREG_X18 U(0x90) 34 #define CTX_GPREG_X19 U(0x98) 35 #define CTX_GPREG_X20 U(0xa0) 36 #define CTX_GPREG_X21 U(0xa8) 37 #define CTX_GPREG_X22 U(0xb0) 38 #define CTX_GPREG_X23 U(0xb8) 39 #define CTX_GPREG_X24 U(0xc0) 40 #define CTX_GPREG_X25 U(0xc8) 41 #define CTX_GPREG_X26 U(0xd0) 42 #define CTX_GPREG_X27 U(0xd8) 43 #define CTX_GPREG_X28 U(0xe0) 44 #define CTX_GPREG_X29 U(0xe8) 45 #define CTX_GPREG_LR U(0xf0) 46 #define CTX_GPREG_SP_EL0 U(0xf8) 47 #define CTX_GPREGS_END U(0x100) 48 49 /******************************************************************************* 50 * Constants that allow assembler code to access members of and the 'el3_state' 51 * structure at their correct offsets. Note that some of the registers are only 52 * 32-bits wide but are stored as 64-bit values for convenience 53 ******************************************************************************/ 54 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 55 #define CTX_SCR_EL3 U(0x0) 56 #define CTX_RUNTIME_SP U(0x8) 57 #define CTX_SPSR_EL3 U(0x10) 58 #define CTX_ELR_EL3 U(0x18) 59 #define CTX_EL3STATE_END U(0x20) 60 61 /******************************************************************************* 62 * Constants that allow assembler code to access members of and the 63 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 64 * registers are only 32-bits wide but are stored as 64-bit values for 65 * convenience 66 ******************************************************************************/ 67 #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 68 #define CTX_SPSR_EL1 U(0x0) 69 #define CTX_ELR_EL1 U(0x8) 70 #define CTX_SCTLR_EL1 U(0x10) 71 #define CTX_ACTLR_EL1 U(0x18) 72 #define CTX_CPACR_EL1 U(0x20) 73 #define CTX_CSSELR_EL1 U(0x28) 74 #define CTX_SP_EL1 U(0x30) 75 #define CTX_ESR_EL1 U(0x38) 76 #define CTX_TTBR0_EL1 U(0x40) 77 #define CTX_TTBR1_EL1 U(0x48) 78 #define CTX_MAIR_EL1 U(0x50) 79 #define CTX_AMAIR_EL1 U(0x58) 80 #define CTX_TCR_EL1 U(0x60) 81 #define CTX_TPIDR_EL1 U(0x68) 82 #define CTX_TPIDR_EL0 U(0x70) 83 #define CTX_TPIDRRO_EL0 U(0x78) 84 #define CTX_PAR_EL1 U(0x80) 85 #define CTX_FAR_EL1 U(0x88) 86 #define CTX_AFSR0_EL1 U(0x90) 87 #define CTX_AFSR1_EL1 U(0x98) 88 #define CTX_CONTEXTIDR_EL1 U(0xa0) 89 #define CTX_VBAR_EL1 U(0xa8) 90 91 /* 92 * If the platform is AArch64-only, there is no need to save and restore these 93 * AArch32 registers. 94 */ 95 #if CTX_INCLUDE_AARCH32_REGS 96 #define CTX_SPSR_ABT U(0xb0) 97 #define CTX_SPSR_UND U(0xb8) 98 #define CTX_SPSR_IRQ U(0xc0) 99 #define CTX_SPSR_FIQ U(0xc8) 100 #define CTX_DACR32_EL2 U(0xd0) 101 #define CTX_IFSR32_EL2 U(0xd8) 102 #define CTX_FP_FPEXC32_EL2 U(0xe0) 103 #define CTX_TIMER_SYSREGS_OFF U(0xf0) /* Align to the next 16 byte boundary */ 104 #else 105 #define CTX_TIMER_SYSREGS_OFF U(0xb0) 106 #endif /* __CTX_INCLUDE_AARCH32_REGS__ */ 107 108 /* 109 * If the timer registers aren't saved and restored, we don't have to reserve 110 * space for them in the context 111 */ 112 #if NS_TIMER_SWITCH 113 #define CTX_CNTP_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x0)) 114 #define CTX_CNTP_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x8)) 115 #define CTX_CNTV_CTL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x10)) 116 #define CTX_CNTV_CVAL_EL0 (CTX_TIMER_SYSREGS_OFF + U(0x18)) 117 #define CTX_CNTKCTL_EL1 (CTX_TIMER_SYSREGS_OFF + U(0x20)) 118 #define CTX_SYSREGS_END (CTX_TIMER_SYSREGS_OFF + U(0x30)) /* Align to the next 16 byte boundary */ 119 #else 120 #define CTX_SYSREGS_END CTX_TIMER_SYSREGS_OFF 121 #endif /* __NS_TIMER_SWITCH__ */ 122 123 /******************************************************************************* 124 * Constants that allow assembler code to access members of and the 'fp_regs' 125 * structure at their correct offsets. 126 ******************************************************************************/ 127 #if CTX_INCLUDE_FPREGS 128 #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) 129 #define CTX_FP_Q0 U(0x0) 130 #define CTX_FP_Q1 U(0x10) 131 #define CTX_FP_Q2 U(0x20) 132 #define CTX_FP_Q3 U(0x30) 133 #define CTX_FP_Q4 U(0x40) 134 #define CTX_FP_Q5 U(0x50) 135 #define CTX_FP_Q6 U(0x60) 136 #define CTX_FP_Q7 U(0x70) 137 #define CTX_FP_Q8 U(0x80) 138 #define CTX_FP_Q9 U(0x90) 139 #define CTX_FP_Q10 U(0xa0) 140 #define CTX_FP_Q11 U(0xb0) 141 #define CTX_FP_Q12 U(0xc0) 142 #define CTX_FP_Q13 U(0xd0) 143 #define CTX_FP_Q14 U(0xe0) 144 #define CTX_FP_Q15 U(0xf0) 145 #define CTX_FP_Q16 U(0x100) 146 #define CTX_FP_Q17 U(0x110) 147 #define CTX_FP_Q18 U(0x120) 148 #define CTX_FP_Q19 U(0x130) 149 #define CTX_FP_Q20 U(0x140) 150 #define CTX_FP_Q21 U(0x150) 151 #define CTX_FP_Q22 U(0x160) 152 #define CTX_FP_Q23 U(0x170) 153 #define CTX_FP_Q24 U(0x180) 154 #define CTX_FP_Q25 U(0x190) 155 #define CTX_FP_Q26 U(0x1a0) 156 #define CTX_FP_Q27 U(0x1b0) 157 #define CTX_FP_Q28 U(0x1c0) 158 #define CTX_FP_Q29 U(0x1d0) 159 #define CTX_FP_Q30 U(0x1e0) 160 #define CTX_FP_Q31 U(0x1f0) 161 #define CTX_FP_FPSR U(0x200) 162 #define CTX_FP_FPCR U(0x208) 163 #define CTX_FPREGS_END U(0x210) 164 #endif 165 166 #ifndef __ASSEMBLY__ 167 168 #include <cassert.h> 169 #include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */ 170 #include <stdint.h> 171 172 /* 173 * Common constants to help define the 'cpu_context' structure and its 174 * members below. 175 */ 176 #define DWORD_SHIFT U(3) 177 #define DEFINE_REG_STRUCT(name, num_regs) \ 178 typedef struct name { \ 179 uint64_t _regs[num_regs]; \ 180 } __aligned(16) name##_t 181 182 /* Constants to determine the size of individual context structures */ 183 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 184 #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) 185 #if CTX_INCLUDE_FPREGS 186 #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 187 #endif 188 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 189 190 /* 191 * AArch64 general purpose register context structure. Usually x0-x18, 192 * lr are saved as the compiler is expected to preserve the remaining 193 * callee saved registers if used by the C runtime and the assembler 194 * does not touch the remaining. But in case of world switch during 195 * exception handling, we need to save the callee registers too. 196 */ 197 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 198 199 /* 200 * AArch64 EL1 system register context structure for preserving the 201 * architectural state during switches from one security state to 202 * another in EL1. 203 */ 204 DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); 205 206 /* 207 * AArch64 floating point register context structure for preserving 208 * the floating point state during switches from one security state to 209 * another. 210 */ 211 #if CTX_INCLUDE_FPREGS 212 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 213 #endif 214 215 /* 216 * Miscellaneous registers used by EL3 firmware to maintain its state 217 * across exception entries and exits 218 */ 219 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 220 221 /* 222 * Macros to access members of any of the above structures using their 223 * offsets 224 */ 225 #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) 226 #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ 227 = val) 228 229 /* 230 * Top-level context structure which is used by EL3 firmware to 231 * preserve the state of a core at EL1 in one of the two security 232 * states and save enough EL3 meta data to be able to return to that 233 * EL and security state. The context management library will be used 234 * to ensure that SP_EL3 always points to an instance of this 235 * structure at exception entry and exit. Each instance will 236 * correspond to either the secure or the non-secure state. 237 */ 238 typedef struct cpu_context { 239 gp_regs_t gpregs_ctx; 240 el3_state_t el3state_ctx; 241 el1_sys_regs_t sysregs_ctx; 242 #if CTX_INCLUDE_FPREGS 243 fp_regs_t fpregs_ctx; 244 #endif 245 } cpu_context_t; 246 247 /* Macros to access members of the 'cpu_context_t' structure */ 248 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 249 #if CTX_INCLUDE_FPREGS 250 #define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 251 #endif 252 #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) 253 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 254 255 /* 256 * Compile time assertions related to the 'cpu_context' structure to 257 * ensure that the assembler and the compiler view of the offsets of 258 * the structure members is the same. 259 */ 260 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 261 assert_core_context_gp_offset_mismatch); 262 CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ 263 assert_core_context_sys_offset_mismatch); 264 #if CTX_INCLUDE_FPREGS 265 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 266 assert_core_context_fp_offset_mismatch); 267 #endif 268 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 269 assert_core_context_el3state_offset_mismatch); 270 271 /* 272 * Helper macro to set the general purpose registers that correspond to 273 * parameters in an aapcs_64 call i.e. x0-x7 274 */ 275 #define set_aapcs_args0(ctx, x0) do { \ 276 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 277 } while (0) 278 #define set_aapcs_args1(ctx, x0, x1) do { \ 279 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 280 set_aapcs_args0(ctx, x0); \ 281 } while (0) 282 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 283 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 284 set_aapcs_args1(ctx, x0, x1); \ 285 } while (0) 286 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 287 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 288 set_aapcs_args2(ctx, x0, x1, x2); \ 289 } while (0) 290 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 291 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 292 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 293 } while (0) 294 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 295 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 296 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 297 } while (0) 298 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 299 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 300 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 301 } while (0) 302 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 303 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 304 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 305 } while (0) 306 307 /******************************************************************************* 308 * Function prototypes 309 ******************************************************************************/ 310 void el1_sysregs_context_save(el1_sys_regs_t *regs); 311 void el1_sysregs_context_restore(el1_sys_regs_t *regs); 312 #if CTX_INCLUDE_FPREGS 313 void fpregs_context_save(fp_regs_t *regs); 314 void fpregs_context_restore(fp_regs_t *regs); 315 #endif 316 317 318 #undef CTX_SYSREG_ALL 319 #if CTX_INCLUDE_FPREGS 320 #undef CTX_FPREG_ALL 321 #endif 322 #undef CTX_GPREG_ALL 323 #undef CTX_EL3STATE_ALL 324 325 #endif /* __ASSEMBLY__ */ 326 327 #endif /* __CONTEXT_H__ */ 328