1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 11 #include <lib/el3_runtime/context_el2.h> 12 #else 13 /** 14 * El1 context is required either when: 15 * IMAGE_BL1 || ((!CTX_INCLUDE_EL2_REGS) && IMAGE_BL31) 16 */ 17 #include <lib/el3_runtime/context_el1.h> 18 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */ 19 20 #include <lib/el3_runtime/cpu_data.h> 21 #include <lib/el3_runtime/simd_ctx.h> 22 #include <lib/utils_def.h> 23 24 /******************************************************************************* 25 * Constants that allow assembler code to access members of and the 'gp_regs' 26 * structure at their correct offsets. 27 ******************************************************************************/ 28 #define CTX_GPREGS_OFFSET U(0x0) 29 #define CTX_GPREG_X0 U(0x0) 30 #define CTX_GPREG_X1 U(0x8) 31 #define CTX_GPREG_X2 U(0x10) 32 #define CTX_GPREG_X3 U(0x18) 33 #define CTX_GPREG_X4 U(0x20) 34 #define CTX_GPREG_X5 U(0x28) 35 #define CTX_GPREG_X6 U(0x30) 36 #define CTX_GPREG_X7 U(0x38) 37 #define CTX_GPREG_X8 U(0x40) 38 #define CTX_GPREG_X9 U(0x48) 39 #define CTX_GPREG_X10 U(0x50) 40 #define CTX_GPREG_X11 U(0x58) 41 #define CTX_GPREG_X12 U(0x60) 42 #define CTX_GPREG_X13 U(0x68) 43 #define CTX_GPREG_X14 U(0x70) 44 #define CTX_GPREG_X15 U(0x78) 45 #define CTX_GPREG_X16 U(0x80) 46 #define CTX_GPREG_X17 U(0x88) 47 #define CTX_GPREG_X18 U(0x90) 48 #define CTX_GPREG_X19 U(0x98) 49 #define CTX_GPREG_X20 U(0xa0) 50 #define CTX_GPREG_X21 U(0xa8) 51 #define CTX_GPREG_X22 U(0xb0) 52 #define CTX_GPREG_X23 U(0xb8) 53 #define CTX_GPREG_X24 U(0xc0) 54 #define CTX_GPREG_X25 U(0xc8) 55 #define CTX_GPREG_X26 U(0xd0) 56 #define CTX_GPREG_X27 U(0xd8) 57 #define CTX_GPREG_X28 U(0xe0) 58 #define CTX_GPREG_X29 U(0xe8) 59 #define CTX_GPREG_LR U(0xf0) 60 #define CTX_GPREG_SP_EL0 U(0xf8) 61 #define CTX_GPREGS_END U(0x100) 62 63 /******************************************************************************* 64 * Constants that allow assembler code to access members of and the 'el3_state' 65 * structure at their correct offsets. Note that some of the registers are only 66 * 32-bits wide but are stored as 64-bit values for convenience 67 ******************************************************************************/ 68 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 69 #define CTX_SCR_EL3 U(0x0) 70 #define CTX_RUNTIME_SP U(0x8) 71 #define CTX_SPSR_EL3 U(0x10) 72 #define CTX_ELR_EL3 U(0x18) 73 #define CTX_PMCR_EL0 U(0x20) 74 #define CTX_IS_IN_EL3 U(0x28) 75 #define CTX_MDCR_EL3 U(0x30) 76 /* Constants required in supporting nested exception in EL3 */ 77 #define CTX_SAVED_ELR_EL3 U(0x38) 78 /* 79 * General purpose flag, to save various EL3 states 80 * FFH mode : Used to identify if handling nested exception 81 * KFH mode : Used as counter value 82 */ 83 #define CTX_NESTED_EA_FLAG U(0x40) 84 #if FFH_SUPPORT 85 #define CTX_SAVED_ESR_EL3 U(0x48) 86 #define CTX_SAVED_SPSR_EL3 U(0x50) 87 #define CTX_SAVED_GPREG_LR U(0x58) 88 #define CTX_DOUBLE_FAULT_ESR U(0x60) 89 #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */ 90 #else 91 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 92 #endif /* FFH_SUPPORT */ 93 94 95 /******************************************************************************* 96 * Registers related to CVE-2018-3639 97 ******************************************************************************/ 98 #define CTX_CVE_2018_3639_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 99 #define CTX_CVE_2018_3639_DISABLE U(0) 100 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 101 102 /******************************************************************************* 103 * Registers related to ERRATA_SPECULATIVE_AT 104 * 105 * This is essential as with EL1 and EL2 context registers being decoupled, 106 * both will not be present for a given build configuration. 107 * As ERRATA_SPECULATIVE_AT errata requires SCTLR_EL1 and TCR_EL1 registers 108 * independent of the above logic, we need explicit context entries to be 109 * reserved for these registers. 110 * 111 * NOTE: Based on this we end up with following different configurations depending 112 * on the presence of errata and inclusion of EL1 or EL2 context. 113 * 114 * ============================================================================ 115 * | ERRATA_SPECULATIVE_AT | EL1 context| Memory allocation(Sctlr_el1,Tcr_el1)| 116 * ============================================================================ 117 * | 0 | 0 | None | 118 * | 0 | 1 | EL1 C-Context structure | 119 * | 1 | 0 | Errata Context Offset Entries | 120 * | 1 | 1 | Errata Context Offset Entries | 121 * ============================================================================ 122 * 123 * In the above table, when ERRATA_SPECULATIVE_AT=1, EL1_Context=0, it implies 124 * there is only EL2 context and memory for SCTLR_EL1 and TCR_EL1 registers is 125 * reserved explicitly under ERRATA_SPECULATIVE_AT build flag here. 126 * 127 * In situations when EL1_Context=1 and ERRATA_SPECULATIVE_AT=1, since SCTLR_EL1 128 * and TCR_EL1 registers will be modified under errata and it happens at the 129 * early in the codeflow prior to el1 context (save and restore operations), 130 * context memory still will be reserved under the errata logic here explicitly. 131 * These registers will not be part of EL1 context save & restore routines. 132 * 133 * Only when ERRATA_SPECULATIVE_AT=0, EL1_Context=1, for this combination, 134 * SCTLR_EL1 and TCR_EL1 will be part of EL1 context structure (context_el1.h) 135 * ----------------------------------------------------------------------------- 136 ******************************************************************************/ 137 #define CTX_ERRATA_SPEC_AT_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 138 #if ERRATA_SPECULATIVE_AT 139 #define CTX_ERRATA_SPEC_AT_SCTLR_EL1 U(0x0) 140 #define CTX_ERRATA_SPEC_AT_TCR_EL1 U(0x8) 141 #define CTX_ERRATA_SPEC_AT_END U(0x10) /* Align to the next 16 byte boundary */ 142 #else 143 #define CTX_ERRATA_SPEC_AT_END U(0x0) 144 #endif /* ERRATA_SPECULATIVE_AT */ 145 146 /******************************************************************************* 147 * Registers related to ARMv8.3-PAuth. 148 ******************************************************************************/ 149 #define CTX_PAUTH_REGS_OFFSET (CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_END) 150 #if CTX_INCLUDE_PAUTH_REGS 151 #define CTX_PACIAKEY_LO U(0x0) 152 #define CTX_PACIAKEY_HI U(0x8) 153 #define CTX_PACIBKEY_LO U(0x10) 154 #define CTX_PACIBKEY_HI U(0x18) 155 #define CTX_PACDAKEY_LO U(0x20) 156 #define CTX_PACDAKEY_HI U(0x28) 157 #define CTX_PACDBKEY_LO U(0x30) 158 #define CTX_PACDBKEY_HI U(0x38) 159 #define CTX_PACGAKEY_LO U(0x40) 160 #define CTX_PACGAKEY_HI U(0x48) 161 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 162 #else 163 #define CTX_PAUTH_REGS_END U(0) 164 #endif /* CTX_INCLUDE_PAUTH_REGS */ 165 166 /******************************************************************************* 167 * Registers initialised in a per-world context. 168 ******************************************************************************/ 169 #define CTX_CPTR_EL3 U(0x0) 170 #define CTX_MPAM3_EL3 U(0x8) 171 #define CTX_PERWORLD_EL3STATE_END U(0x10) 172 173 #ifndef __ASSEMBLER__ 174 175 #include <stdint.h> 176 177 #include <lib/cassert.h> 178 179 /* 180 * Common constants to help define the 'cpu_context' structure and its 181 * members below. 182 */ 183 #define DWORD_SHIFT U(3) 184 #define DEFINE_REG_STRUCT(name, num_regs) \ 185 typedef struct name { \ 186 uint64_t ctx_regs[num_regs]; \ 187 } __aligned(16) name##_t 188 189 /* Constants to determine the size of individual context structures */ 190 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 191 192 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 193 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 194 195 #if ERRATA_SPECULATIVE_AT 196 #define CTX_ERRATA_SPEC_AT_ALL (CTX_ERRATA_SPEC_AT_END >> DWORD_SHIFT) 197 #endif 198 #if CTX_INCLUDE_PAUTH_REGS 199 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 200 #endif 201 202 /* 203 * AArch64 general purpose register context structure. Usually x0-x18, 204 * lr are saved as the compiler is expected to preserve the remaining 205 * callee saved registers if used by the C runtime and the assembler 206 * does not touch the remaining. But in case of world switch during 207 * exception handling, we need to save the callee registers too. 208 */ 209 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 210 211 /* 212 * Miscellaneous registers used by EL3 firmware to maintain its state 213 * across exception entries and exits 214 */ 215 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 216 217 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 218 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 219 220 /* Registers associated to Errata_Speculative */ 221 #if ERRATA_SPECULATIVE_AT 222 DEFINE_REG_STRUCT(errata_speculative_at, CTX_ERRATA_SPEC_AT_ALL); 223 #endif 224 225 /* Registers associated to ARMv8.3-PAuth */ 226 #if CTX_INCLUDE_PAUTH_REGS 227 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 228 #endif 229 230 /* 231 * Macros to access members of any of the above structures using their 232 * offsets 233 */ 234 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 235 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 236 = (uint64_t) (val)) 237 238 /* 239 * Top-level context structure which is used by EL3 firmware to preserve 240 * the state of a core at the next lower EL in a given security state and 241 * save enough EL3 meta data to be able to return to that EL and security 242 * state. The context management library will be used to ensure that 243 * SP_EL3 always points to an instance of this structure at exception 244 * entry and exit. 245 */ 246 typedef struct cpu_context { 247 gp_regs_t gpregs_ctx; 248 el3_state_t el3state_ctx; 249 250 cve_2018_3639_t cve_2018_3639_ctx; 251 252 #if ERRATA_SPECULATIVE_AT 253 errata_speculative_at_t errata_speculative_at_ctx; 254 #endif 255 256 #if CTX_INCLUDE_PAUTH_REGS 257 pauth_t pauth_ctx; 258 #endif 259 260 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 261 el2_sysregs_t el2_sysregs_ctx; 262 #else 263 /* El1 context should be included only either for IMAGE_BL1, 264 * or for IMAGE_BL31 when CTX_INCLUDE_EL2_REGS=0: 265 * When SPMD_SPM_AT_SEL2=1, SPMC at S-EL2 takes care of saving 266 * and restoring EL1 registers. In this case, BL31 at EL3 can 267 * exclude save and restore of EL1 context registers. 268 */ 269 el1_sysregs_t el1_sysregs_ctx; 270 #endif 271 272 } cpu_context_t; 273 274 /* 275 * Per-World Context. 276 * It stores registers whose values can be shared across CPUs. 277 */ 278 typedef struct per_world_context { 279 uint64_t ctx_cptr_el3; 280 uint64_t ctx_mpam3_el3; 281 } per_world_context_t; 282 283 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 284 285 /* Macros to access members of the 'cpu_context_t' structure */ 286 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 287 288 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) 289 #define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 290 #else 291 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 292 #endif 293 294 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 295 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 296 297 #if ERRATA_SPECULATIVE_AT 298 #define get_errata_speculative_at_ctx(h) (&((cpu_context_t *) h)->errata_speculative_at_ctx) 299 #endif 300 301 #if CTX_INCLUDE_PAUTH_REGS 302 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 303 #endif 304 305 /* 306 * Compile time assertions related to the 'cpu_context' structure to 307 * ensure that the assembler and the compiler view of the offsets of 308 * the structure members is the same. 309 */ 310 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 311 assert_core_context_gp_offset_mismatch); 312 313 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 314 assert_core_context_el3state_offset_mismatch); 315 316 317 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 318 assert_core_context_cve_2018_3639_offset_mismatch); 319 320 #if ERRATA_SPECULATIVE_AT 321 CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx), 322 assert_core_context_errata_speculative_at_offset_mismatch); 323 #endif 324 325 #if CTX_INCLUDE_PAUTH_REGS 326 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 327 assert_core_context_pauth_offset_mismatch); 328 #endif /* CTX_INCLUDE_PAUTH_REGS */ 329 330 /* 331 * Helper macro to set the general purpose registers that correspond to 332 * parameters in an aapcs_64 call i.e. x0-x7 333 */ 334 #define set_aapcs_args0(ctx, x0) do { \ 335 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 336 } while (0) 337 #define set_aapcs_args1(ctx, x0, x1) do { \ 338 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 339 set_aapcs_args0(ctx, x0); \ 340 } while (0) 341 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 342 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 343 set_aapcs_args1(ctx, x0, x1); \ 344 } while (0) 345 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 346 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 347 set_aapcs_args2(ctx, x0, x1, x2); \ 348 } while (0) 349 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 350 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 351 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 352 } while (0) 353 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 354 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 355 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 356 } while (0) 357 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 358 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 359 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 360 } while (0) 361 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 362 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 363 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 364 } while (0) 365 366 /******************************************************************************* 367 * Function prototypes 368 ******************************************************************************/ 369 #if CTX_INCLUDE_FPREGS 370 void fpregs_context_save(simd_regs_t *regs); 371 void fpregs_context_restore(simd_regs_t *regs); 372 #endif 373 374 /******************************************************************************* 375 * The next four inline functions are required for IMAGE_BL1, as well as for 376 * IMAGE_BL31 for the below combinations. 377 * ============================================================================ 378 * | ERRATA_SPECULATIVE_AT| CTX_INCLUDE_EL2_REGS | Combination | 379 * ============================================================================ 380 * | 0 | 0 | Valid (EL1 ctx) | 381 * |______________________|______________________|____________________________| 382 * | | | Invalid (No Errata/EL1 Ctx)| 383 * | 0 | 1 | Hence commented out. | 384 * |______________________|______________________|____________________________| 385 * | | | | 386 * | 1 | 0 | Valid (Errata ctx) | 387 * |______________________|______________________|____________________________| 388 * | | | | 389 * | 1 | 1 | Valid (Errata ctx) | 390 * |______________________|______________________|____________________________| 391 * ============================================================================ 392 ******************************************************************************/ 393 #if (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) 394 395 static inline void write_ctx_sctlr_el1_reg_errata(cpu_context_t *ctx, u_register_t val) 396 { 397 #if (ERRATA_SPECULATIVE_AT) 398 write_ctx_reg(get_errata_speculative_at_ctx(ctx), 399 CTX_ERRATA_SPEC_AT_SCTLR_EL1, val); 400 #else 401 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1, val); 402 #endif /* ERRATA_SPECULATIVE_AT */ 403 } 404 405 static inline void write_ctx_tcr_el1_reg_errata(cpu_context_t *ctx, u_register_t val) 406 { 407 #if (ERRATA_SPECULATIVE_AT) 408 write_ctx_reg(get_errata_speculative_at_ctx(ctx), 409 CTX_ERRATA_SPEC_AT_TCR_EL1, val); 410 #else 411 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1, val); 412 #endif /* ERRATA_SPECULATIVE_AT */ 413 } 414 415 static inline u_register_t read_ctx_sctlr_el1_reg_errata(cpu_context_t *ctx) 416 { 417 #if (ERRATA_SPECULATIVE_AT) 418 return read_ctx_reg(get_errata_speculative_at_ctx(ctx), 419 CTX_ERRATA_SPEC_AT_SCTLR_EL1); 420 #else 421 return read_el1_ctx_common(get_el1_sysregs_ctx(ctx), sctlr_el1); 422 #endif /* ERRATA_SPECULATIVE_AT */ 423 } 424 425 static inline u_register_t read_ctx_tcr_el1_reg_errata(cpu_context_t *ctx) 426 { 427 #if (ERRATA_SPECULATIVE_AT) 428 return read_ctx_reg(get_errata_speculative_at_ctx(ctx), 429 CTX_ERRATA_SPEC_AT_TCR_EL1); 430 #else 431 return read_el1_ctx_common(get_el1_sysregs_ctx(ctx), tcr_el1); 432 #endif /* ERRATA_SPECULATIVE_AT */ 433 } 434 435 #endif /* (IMAGE_BL1 || ((ERRATA_SPECULATIVE_AT) || (!CTX_INCLUDE_EL2_REGS))) */ 436 437 #endif /* __ASSEMBLER__ */ 438 439 #endif /* CONTEXT_H */ 440