1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Constants that allow assembler code to access members of and the 'gp_regs' 14 * structure at their correct offsets. 15 ******************************************************************************/ 16 #define CTX_GPREGS_OFFSET U(0x0) 17 #define CTX_GPREG_X0 U(0x0) 18 #define CTX_GPREG_X1 U(0x8) 19 #define CTX_GPREG_X2 U(0x10) 20 #define CTX_GPREG_X3 U(0x18) 21 #define CTX_GPREG_X4 U(0x20) 22 #define CTX_GPREG_X5 U(0x28) 23 #define CTX_GPREG_X6 U(0x30) 24 #define CTX_GPREG_X7 U(0x38) 25 #define CTX_GPREG_X8 U(0x40) 26 #define CTX_GPREG_X9 U(0x48) 27 #define CTX_GPREG_X10 U(0x50) 28 #define CTX_GPREG_X11 U(0x58) 29 #define CTX_GPREG_X12 U(0x60) 30 #define CTX_GPREG_X13 U(0x68) 31 #define CTX_GPREG_X14 U(0x70) 32 #define CTX_GPREG_X15 U(0x78) 33 #define CTX_GPREG_X16 U(0x80) 34 #define CTX_GPREG_X17 U(0x88) 35 #define CTX_GPREG_X18 U(0x90) 36 #define CTX_GPREG_X19 U(0x98) 37 #define CTX_GPREG_X20 U(0xa0) 38 #define CTX_GPREG_X21 U(0xa8) 39 #define CTX_GPREG_X22 U(0xb0) 40 #define CTX_GPREG_X23 U(0xb8) 41 #define CTX_GPREG_X24 U(0xc0) 42 #define CTX_GPREG_X25 U(0xc8) 43 #define CTX_GPREG_X26 U(0xd0) 44 #define CTX_GPREG_X27 U(0xd8) 45 #define CTX_GPREG_X28 U(0xe0) 46 #define CTX_GPREG_X29 U(0xe8) 47 #define CTX_GPREG_LR U(0xf0) 48 #define CTX_GPREG_SP_EL0 U(0xf8) 49 #define CTX_GPREGS_END U(0x100) 50 51 /******************************************************************************* 52 * Constants that allow assembler code to access members of and the 'el3_state' 53 * structure at their correct offsets. Note that some of the registers are only 54 * 32-bits wide but are stored as 64-bit values for convenience 55 ******************************************************************************/ 56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 57 #define CTX_SCR_EL3 U(0x0) 58 #define CTX_ESR_EL3 U(0x8) 59 #define CTX_RUNTIME_SP U(0x10) 60 #define CTX_SPSR_EL3 U(0x18) 61 #define CTX_ELR_EL3 U(0x20) 62 #define CTX_PMCR_EL0 U(0x28) 63 #define CTX_EL3STATE_END U(0x30) 64 65 /******************************************************************************* 66 * Constants that allow assembler code to access members of and the 67 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 68 * registers are only 32-bits wide but are stored as 64-bit values for 69 * convenience 70 ******************************************************************************/ 71 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 72 #define CTX_SPSR_EL1 U(0x0) 73 #define CTX_ELR_EL1 U(0x8) 74 #define CTX_SCTLR_EL1 U(0x10) 75 #define CTX_ACTLR_EL1 U(0x18) 76 #define CTX_CPACR_EL1 U(0x20) 77 #define CTX_CSSELR_EL1 U(0x28) 78 #define CTX_SP_EL1 U(0x30) 79 #define CTX_ESR_EL1 U(0x38) 80 #define CTX_TTBR0_EL1 U(0x40) 81 #define CTX_TTBR1_EL1 U(0x48) 82 #define CTX_MAIR_EL1 U(0x50) 83 #define CTX_AMAIR_EL1 U(0x58) 84 #define CTX_TCR_EL1 U(0x60) 85 #define CTX_TPIDR_EL1 U(0x68) 86 #define CTX_TPIDR_EL0 U(0x70) 87 #define CTX_TPIDRRO_EL0 U(0x78) 88 #define CTX_PAR_EL1 U(0x80) 89 #define CTX_FAR_EL1 U(0x88) 90 #define CTX_AFSR0_EL1 U(0x90) 91 #define CTX_AFSR1_EL1 U(0x98) 92 #define CTX_CONTEXTIDR_EL1 U(0xa0) 93 #define CTX_VBAR_EL1 U(0xa8) 94 95 /* 96 * If the platform is AArch64-only, there is no need to save and restore these 97 * AArch32 registers. 98 */ 99 #if CTX_INCLUDE_AARCH32_REGS 100 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 101 #define CTX_SPSR_UND U(0xb8) 102 #define CTX_SPSR_IRQ U(0xc0) 103 #define CTX_SPSR_FIQ U(0xc8) 104 #define CTX_DACR32_EL2 U(0xd0) 105 #define CTX_IFSR32_EL2 U(0xd8) 106 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 107 #else 108 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 109 #endif /* CTX_INCLUDE_AARCH32_REGS */ 110 111 /* 112 * If the timer registers aren't saved and restored, we don't have to reserve 113 * space for them in the context 114 */ 115 #if NS_TIMER_SWITCH 116 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 117 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 118 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 119 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 120 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 121 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 122 #else 123 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 124 #endif /* NS_TIMER_SWITCH */ 125 126 #if CTX_INCLUDE_MTE_REGS 127 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 128 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 129 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 130 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 131 132 /* Align to the next 16 byte boundary */ 133 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 134 #else 135 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* 139 * End of system registers. 140 */ 141 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 142 143 /* 144 * EL2 register set 145 */ 146 147 #if CTX_INCLUDE_EL2_REGS 148 /* For later discussion 149 * ICH_AP0R<n>_EL2 150 * ICH_AP1R<n>_EL2 151 * AMEVCNTVOFF0<n>_EL2 152 * AMEVCNTVOFF1<n>_EL2 153 * ICH_LR<n>_EL2 154 */ 155 #define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 156 157 #define CTX_ACTLR_EL2 U(0x0) 158 #define CTX_AFSR0_EL2 U(0x8) 159 #define CTX_AFSR1_EL2 U(0x10) 160 #define CTX_AMAIR_EL2 U(0x18) 161 #define CTX_CNTHCTL_EL2 U(0x20) 162 #define CTX_CNTHP_CTL_EL2 U(0x28) 163 #define CTX_CNTHP_CVAL_EL2 U(0x30) 164 #define CTX_CNTHP_TVAL_EL2 U(0x38) 165 #define CTX_CNTVOFF_EL2 U(0x40) 166 #define CTX_CPTR_EL2 U(0x48) 167 #define CTX_DBGVCR32_EL2 U(0x50) 168 #define CTX_ELR_EL2 U(0x58) 169 #define CTX_ESR_EL2 U(0x60) 170 #define CTX_FAR_EL2 U(0x68) 171 #define CTX_FPEXC32_EL2 U(0x70) 172 #define CTX_HACR_EL2 U(0x78) 173 #define CTX_HCR_EL2 U(0x80) 174 #define CTX_HPFAR_EL2 U(0x88) 175 #define CTX_HSTR_EL2 U(0x90) 176 #define CTX_ICC_SRE_EL2 U(0x98) 177 #define CTX_ICH_HCR_EL2 U(0xa0) 178 #define CTX_ICH_VMCR_EL2 U(0xa8) 179 #define CTX_MAIR_EL2 U(0xb0) 180 #define CTX_MDCR_EL2 U(0xb8) 181 #define CTX_PMSCR_EL2 U(0xc0) 182 #define CTX_SCTLR_EL2 U(0xc8) 183 #define CTX_SPSR_EL2 U(0xd0) 184 #define CTX_SP_EL2 U(0xd8) 185 #define CTX_TCR_EL2 U(0xe0) 186 #define CTX_TRFCR_EL2 U(0xe8) 187 #define CTX_TTBR0_EL2 U(0xf0) 188 #define CTX_VBAR_EL2 U(0xf8) 189 #define CTX_VMPIDR_EL2 U(0x100) 190 #define CTX_VPIDR_EL2 U(0x108) 191 #define CTX_VTCR_EL2 U(0x110) 192 #define CTX_VTTBR_EL2 U(0x118) 193 194 // Only if MTE registers in use 195 #define CTX_TFSR_EL2 U(0x120) 196 197 // Only if ENABLE_MPAM_FOR_LOWER_ELS==1 198 #define CTX_MPAM2_EL2 U(0x128) 199 #define CTX_MPAMHCR_EL2 U(0x130) 200 #define CTX_MPAMVPM0_EL2 U(0x138) 201 #define CTX_MPAMVPM1_EL2 U(0x140) 202 #define CTX_MPAMVPM2_EL2 U(0x148) 203 #define CTX_MPAMVPM3_EL2 U(0x150) 204 #define CTX_MPAMVPM4_EL2 U(0x158) 205 #define CTX_MPAMVPM5_EL2 U(0x160) 206 #define CTX_MPAMVPM6_EL2 U(0x168) 207 #define CTX_MPAMVPM7_EL2 U(0x170) 208 #define CTX_MPAMVPMV_EL2 U(0x178) 209 210 // Starting with Armv8.6 211 #define CTX_HAFGRTR_EL2 U(0x180) 212 #define CTX_HDFGRTR_EL2 U(0x188) 213 #define CTX_HDFGWTR_EL2 U(0x190) 214 #define CTX_HFGITR_EL2 U(0x198) 215 #define CTX_HFGRTR_EL2 U(0x1a0) 216 #define CTX_HFGWTR_EL2 U(0x1a8) 217 #define CTX_CNTPOFF_EL2 U(0x1b0) 218 219 // Starting with Armv8.4 220 #define CTX_CNTHPS_CTL_EL2 U(0x1b8) 221 #define CTX_CNTHPS_CVAL_EL2 U(0x1c0) 222 #define CTX_CNTHPS_TVAL_EL2 U(0x1c8) 223 #define CTX_CNTHVS_CTL_EL2 U(0x1d0) 224 #define CTX_CNTHVS_CVAL_EL2 U(0x1d8) 225 #define CTX_CNTHVS_TVAL_EL2 U(0x1e0) 226 #define CTX_CNTHV_CTL_EL2 U(0x1e8) 227 #define CTX_CNTHV_CVAL_EL2 U(0x1f0) 228 #define CTX_CNTHV_TVAL_EL2 U(0x1f8) 229 #define CTX_CONTEXTIDR_EL2 U(0x200) 230 #define CTX_SDER32_EL2 U(0x208) 231 #define CTX_TTBR1_EL2 U(0x210) 232 #define CTX_VDISR_EL2 U(0x218) 233 #define CTX_VNCR_EL2 U(0x220) 234 #define CTX_VSESR_EL2 U(0x228) 235 #define CTX_VSTCR_EL2 U(0x230) 236 #define CTX_VSTTBR_EL2 U(0x238) 237 238 // Starting with Armv8.5 239 #define CTX_SCXTNUM_EL2 U(0x240) 240 /* Align to the next 16 byte boundary */ 241 #define CTX_EL2_SYSREGS_END U(0x250) 242 #endif /* CTX_INCLUDE_EL2_REGS */ 243 244 /******************************************************************************* 245 * Constants that allow assembler code to access members of and the 'fp_regs' 246 * structure at their correct offsets. 247 ******************************************************************************/ 248 #if CTX_INCLUDE_EL2_REGS 249 # define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) 250 #else 251 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 252 #endif 253 #if CTX_INCLUDE_FPREGS 254 #define CTX_FP_Q0 U(0x0) 255 #define CTX_FP_Q1 U(0x10) 256 #define CTX_FP_Q2 U(0x20) 257 #define CTX_FP_Q3 U(0x30) 258 #define CTX_FP_Q4 U(0x40) 259 #define CTX_FP_Q5 U(0x50) 260 #define CTX_FP_Q6 U(0x60) 261 #define CTX_FP_Q7 U(0x70) 262 #define CTX_FP_Q8 U(0x80) 263 #define CTX_FP_Q9 U(0x90) 264 #define CTX_FP_Q10 U(0xa0) 265 #define CTX_FP_Q11 U(0xb0) 266 #define CTX_FP_Q12 U(0xc0) 267 #define CTX_FP_Q13 U(0xd0) 268 #define CTX_FP_Q14 U(0xe0) 269 #define CTX_FP_Q15 U(0xf0) 270 #define CTX_FP_Q16 U(0x100) 271 #define CTX_FP_Q17 U(0x110) 272 #define CTX_FP_Q18 U(0x120) 273 #define CTX_FP_Q19 U(0x130) 274 #define CTX_FP_Q20 U(0x140) 275 #define CTX_FP_Q21 U(0x150) 276 #define CTX_FP_Q22 U(0x160) 277 #define CTX_FP_Q23 U(0x170) 278 #define CTX_FP_Q24 U(0x180) 279 #define CTX_FP_Q25 U(0x190) 280 #define CTX_FP_Q26 U(0x1a0) 281 #define CTX_FP_Q27 U(0x1b0) 282 #define CTX_FP_Q28 U(0x1c0) 283 #define CTX_FP_Q29 U(0x1d0) 284 #define CTX_FP_Q30 U(0x1e0) 285 #define CTX_FP_Q31 U(0x1f0) 286 #define CTX_FP_FPSR U(0x200) 287 #define CTX_FP_FPCR U(0x208) 288 #if CTX_INCLUDE_AARCH32_REGS 289 #define CTX_FP_FPEXC32_EL2 U(0x210) 290 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 291 #else 292 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 293 #endif 294 #else 295 #define CTX_FPREGS_END U(0) 296 #endif 297 298 /******************************************************************************* 299 * Registers related to CVE-2018-3639 300 ******************************************************************************/ 301 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 302 #define CTX_CVE_2018_3639_DISABLE U(0) 303 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 304 305 /******************************************************************************* 306 * Registers related to ARMv8.3-PAuth. 307 ******************************************************************************/ 308 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 309 #if CTX_INCLUDE_PAUTH_REGS 310 #define CTX_PACIAKEY_LO U(0x0) 311 #define CTX_PACIAKEY_HI U(0x8) 312 #define CTX_PACIBKEY_LO U(0x10) 313 #define CTX_PACIBKEY_HI U(0x18) 314 #define CTX_PACDAKEY_LO U(0x20) 315 #define CTX_PACDAKEY_HI U(0x28) 316 #define CTX_PACDBKEY_LO U(0x30) 317 #define CTX_PACDBKEY_HI U(0x38) 318 #define CTX_PACGAKEY_LO U(0x40) 319 #define CTX_PACGAKEY_HI U(0x48) 320 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 321 #else 322 #define CTX_PAUTH_REGS_END U(0) 323 #endif /* CTX_INCLUDE_PAUTH_REGS */ 324 325 #ifndef __ASSEMBLER__ 326 327 #include <stdint.h> 328 329 #include <lib/cassert.h> 330 331 /* 332 * Common constants to help define the 'cpu_context' structure and its 333 * members below. 334 */ 335 #define DWORD_SHIFT U(3) 336 #define DEFINE_REG_STRUCT(name, num_regs) \ 337 typedef struct name { \ 338 uint64_t ctx_regs[num_regs]; \ 339 } __aligned(16) name##_t 340 341 /* Constants to determine the size of individual context structures */ 342 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 343 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 344 #if CTX_INCLUDE_EL2_REGS 345 # define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) 346 #endif 347 #if CTX_INCLUDE_FPREGS 348 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 349 #endif 350 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 351 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 352 #if CTX_INCLUDE_PAUTH_REGS 353 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 354 #endif 355 356 /* 357 * AArch64 general purpose register context structure. Usually x0-x18, 358 * lr are saved as the compiler is expected to preserve the remaining 359 * callee saved registers if used by the C runtime and the assembler 360 * does not touch the remaining. But in case of world switch during 361 * exception handling, we need to save the callee registers too. 362 */ 363 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 364 365 /* 366 * AArch64 EL1 system register context structure for preserving the 367 * architectural state during world switches. 368 */ 369 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 370 371 372 /* 373 * AArch64 EL2 system register context structure for preserving the 374 * architectural state during world switches. 375 */ 376 #if CTX_INCLUDE_EL2_REGS 377 DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); 378 #endif 379 380 /* 381 * AArch64 floating point register context structure for preserving 382 * the floating point state during switches from one security state to 383 * another. 384 */ 385 #if CTX_INCLUDE_FPREGS 386 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 387 #endif 388 389 /* 390 * Miscellaneous registers used by EL3 firmware to maintain its state 391 * across exception entries and exits 392 */ 393 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 394 395 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 396 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 397 398 /* Registers associated to ARMv8.3-PAuth */ 399 #if CTX_INCLUDE_PAUTH_REGS 400 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 401 #endif 402 403 /* 404 * Macros to access members of any of the above structures using their 405 * offsets 406 */ 407 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 408 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 409 = (uint64_t) (val)) 410 411 /* 412 * Top-level context structure which is used by EL3 firmware to 413 * preserve the state of a core at EL1 in one of the two security 414 * states and save enough EL3 meta data to be able to return to that 415 * EL and security state. The context management library will be used 416 * to ensure that SP_EL3 always points to an instance of this 417 * structure at exception entry and exit. Each instance will 418 * correspond to either the secure or the non-secure state. 419 */ 420 typedef struct cpu_context { 421 gp_regs_t gpregs_ctx; 422 el3_state_t el3state_ctx; 423 el1_sysregs_t el1_sysregs_ctx; 424 #if CTX_INCLUDE_EL2_REGS 425 el2_sysregs_t el2_sysregs_ctx; 426 #endif 427 #if CTX_INCLUDE_FPREGS 428 fp_regs_t fpregs_ctx; 429 #endif 430 cve_2018_3639_t cve_2018_3639_ctx; 431 #if CTX_INCLUDE_PAUTH_REGS 432 pauth_t pauth_ctx; 433 #endif 434 } cpu_context_t; 435 436 /* Macros to access members of the 'cpu_context_t' structure */ 437 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 438 #if CTX_INCLUDE_FPREGS 439 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 440 #endif 441 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 442 #if CTX_INCLUDE_EL2_REGS 443 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 444 #endif 445 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 446 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 447 #if CTX_INCLUDE_PAUTH_REGS 448 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 449 #endif 450 451 /* 452 * Compile time assertions related to the 'cpu_context' structure to 453 * ensure that the assembler and the compiler view of the offsets of 454 * the structure members is the same. 455 */ 456 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 457 assert_core_context_gp_offset_mismatch); 458 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), \ 459 assert_core_context_el1_sys_offset_mismatch); 460 #if CTX_INCLUDE_EL2_REGS 461 CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), \ 462 assert_core_context_el2_sys_offset_mismatch); 463 #endif 464 #if CTX_INCLUDE_FPREGS 465 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 466 assert_core_context_fp_offset_mismatch); 467 #endif 468 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 469 assert_core_context_el3state_offset_mismatch); 470 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ 471 assert_core_context_cve_2018_3639_offset_mismatch); 472 #if CTX_INCLUDE_PAUTH_REGS 473 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ 474 assert_core_context_pauth_offset_mismatch); 475 #endif 476 477 /* 478 * Helper macro to set the general purpose registers that correspond to 479 * parameters in an aapcs_64 call i.e. x0-x7 480 */ 481 #define set_aapcs_args0(ctx, x0) do { \ 482 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 483 } while (0) 484 #define set_aapcs_args1(ctx, x0, x1) do { \ 485 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 486 set_aapcs_args0(ctx, x0); \ 487 } while (0) 488 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 489 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 490 set_aapcs_args1(ctx, x0, x1); \ 491 } while (0) 492 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 493 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 494 set_aapcs_args2(ctx, x0, x1, x2); \ 495 } while (0) 496 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 497 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 498 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 499 } while (0) 500 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 501 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 502 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 503 } while (0) 504 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 505 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 506 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 507 } while (0) 508 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 509 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 510 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 511 } while (0) 512 513 /******************************************************************************* 514 * Function prototypes 515 ******************************************************************************/ 516 void el1_sysregs_context_save(el1_sysregs_t *regs); 517 void el1_sysregs_context_restore(el1_sysregs_t *regs); 518 519 #if CTX_INCLUDE_EL2_REGS 520 void el2_sysregs_context_save(el2_sysregs_t *regs); 521 void el2_sysregs_context_restore(el2_sysregs_t *regs); 522 #endif 523 524 #if CTX_INCLUDE_FPREGS 525 void fpregs_context_save(fp_regs_t *regs); 526 void fpregs_context_restore(fp_regs_t *regs); 527 #endif 528 529 #endif /* __ASSEMBLER__ */ 530 531 #endif /* CONTEXT_H */ 532