1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/el3_runtime/cpu_data.h> 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * Constants that allow assembler code to access members of and the 'gp_regs' 15 * structure at their correct offsets. 16 ******************************************************************************/ 17 #define CTX_GPREGS_OFFSET U(0x0) 18 #define CTX_GPREG_X0 U(0x0) 19 #define CTX_GPREG_X1 U(0x8) 20 #define CTX_GPREG_X2 U(0x10) 21 #define CTX_GPREG_X3 U(0x18) 22 #define CTX_GPREG_X4 U(0x20) 23 #define CTX_GPREG_X5 U(0x28) 24 #define CTX_GPREG_X6 U(0x30) 25 #define CTX_GPREG_X7 U(0x38) 26 #define CTX_GPREG_X8 U(0x40) 27 #define CTX_GPREG_X9 U(0x48) 28 #define CTX_GPREG_X10 U(0x50) 29 #define CTX_GPREG_X11 U(0x58) 30 #define CTX_GPREG_X12 U(0x60) 31 #define CTX_GPREG_X13 U(0x68) 32 #define CTX_GPREG_X14 U(0x70) 33 #define CTX_GPREG_X15 U(0x78) 34 #define CTX_GPREG_X16 U(0x80) 35 #define CTX_GPREG_X17 U(0x88) 36 #define CTX_GPREG_X18 U(0x90) 37 #define CTX_GPREG_X19 U(0x98) 38 #define CTX_GPREG_X20 U(0xa0) 39 #define CTX_GPREG_X21 U(0xa8) 40 #define CTX_GPREG_X22 U(0xb0) 41 #define CTX_GPREG_X23 U(0xb8) 42 #define CTX_GPREG_X24 U(0xc0) 43 #define CTX_GPREG_X25 U(0xc8) 44 #define CTX_GPREG_X26 U(0xd0) 45 #define CTX_GPREG_X27 U(0xd8) 46 #define CTX_GPREG_X28 U(0xe0) 47 #define CTX_GPREG_X29 U(0xe8) 48 #define CTX_GPREG_LR U(0xf0) 49 #define CTX_GPREG_SP_EL0 U(0xf8) 50 #define CTX_GPREGS_END U(0x100) 51 52 /******************************************************************************* 53 * Constants that allow assembler code to access members of and the 'el3_state' 54 * structure at their correct offsets. Note that some of the registers are only 55 * 32-bits wide but are stored as 64-bit values for convenience 56 ******************************************************************************/ 57 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 58 #define CTX_SCR_EL3 U(0x0) 59 #define CTX_ESR_EL3 U(0x8) 60 #define CTX_RUNTIME_SP U(0x10) 61 #define CTX_SPSR_EL3 U(0x18) 62 #define CTX_ELR_EL3 U(0x20) 63 #define CTX_PMCR_EL0 U(0x28) 64 #define CTX_IS_IN_EL3 U(0x30) 65 /* Constants required in supporting nested exception in EL3 */ 66 #define CTX_SAVED_ELR_EL3 U(0x38) 67 /* 68 * General purpose flag, to save various EL3 states 69 * FFH mode : Used to identify if handling nested exception 70 * KFH mode : Used as counter value 71 */ 72 #define CTX_NESTED_EA_FLAG U(0x40) 73 #if FFH_SUPPORT 74 #define CTX_SAVED_ESR_EL3 U(0x48) 75 #define CTX_SAVED_SPSR_EL3 U(0x50) 76 #define CTX_SAVED_GPREG_LR U(0x58) 77 #define CTX_EL3STATE_END U(0x60) /* Align to the next 16 byte boundary */ 78 #else 79 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 80 #endif /* FFH_SUPPORT */ 81 82 /******************************************************************************* 83 * Constants that allow assembler code to access members of and the 84 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 85 * registers are only 32-bits wide but are stored as 64-bit values for 86 * convenience 87 ******************************************************************************/ 88 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 89 #define CTX_SPSR_EL1 U(0x0) 90 #define CTX_ELR_EL1 U(0x8) 91 #define CTX_SCTLR_EL1 U(0x10) 92 #define CTX_TCR_EL1 U(0x18) 93 #define CTX_CPACR_EL1 U(0x20) 94 #define CTX_CSSELR_EL1 U(0x28) 95 #define CTX_SP_EL1 U(0x30) 96 #define CTX_ESR_EL1 U(0x38) 97 #define CTX_TTBR0_EL1 U(0x40) 98 #define CTX_TTBR1_EL1 U(0x48) 99 #define CTX_MAIR_EL1 U(0x50) 100 #define CTX_AMAIR_EL1 U(0x58) 101 #define CTX_ACTLR_EL1 U(0x60) 102 #define CTX_TPIDR_EL1 U(0x68) 103 #define CTX_TPIDR_EL0 U(0x70) 104 #define CTX_TPIDRRO_EL0 U(0x78) 105 #define CTX_PAR_EL1 U(0x80) 106 #define CTX_FAR_EL1 U(0x88) 107 #define CTX_AFSR0_EL1 U(0x90) 108 #define CTX_AFSR1_EL1 U(0x98) 109 #define CTX_CONTEXTIDR_EL1 U(0xa0) 110 #define CTX_VBAR_EL1 U(0xa8) 111 112 /* 113 * If the platform is AArch64-only, there is no need to save and restore these 114 * AArch32 registers. 115 */ 116 #if CTX_INCLUDE_AARCH32_REGS 117 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 118 #define CTX_SPSR_UND U(0xb8) 119 #define CTX_SPSR_IRQ U(0xc0) 120 #define CTX_SPSR_FIQ U(0xc8) 121 #define CTX_DACR32_EL2 U(0xd0) 122 #define CTX_IFSR32_EL2 U(0xd8) 123 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 124 #else 125 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 126 #endif /* CTX_INCLUDE_AARCH32_REGS */ 127 128 /* 129 * If the timer registers aren't saved and restored, we don't have to reserve 130 * space for them in the context 131 */ 132 #if NS_TIMER_SWITCH 133 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 134 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 135 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 136 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 137 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 138 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 139 #else 140 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 141 #endif /* NS_TIMER_SWITCH */ 142 143 #if ENABLE_FEAT_MTE 144 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 145 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 146 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 147 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 148 149 /* Align to the next 16 byte boundary */ 150 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 151 #else 152 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 153 #endif /* ENABLE_FEAT_MTE */ 154 155 /* 156 * End of system registers. 157 */ 158 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 159 160 /* 161 * EL2 register set 162 */ 163 164 #if CTX_INCLUDE_EL2_REGS 165 /* For later discussion 166 * ICH_AP0R<n>_EL2 167 * ICH_AP1R<n>_EL2 168 * AMEVCNTVOFF0<n>_EL2 169 * AMEVCNTVOFF1<n>_EL2 170 * ICH_LR<n>_EL2 171 */ 172 #define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 173 174 #define CTX_ACTLR_EL2 U(0x0) 175 #define CTX_AFSR0_EL2 U(0x8) 176 #define CTX_AFSR1_EL2 U(0x10) 177 #define CTX_AMAIR_EL2 U(0x18) 178 #define CTX_CNTHCTL_EL2 U(0x20) 179 #define CTX_CNTVOFF_EL2 U(0x28) 180 #define CTX_CPTR_EL2 U(0x30) 181 #define CTX_DBGVCR32_EL2 U(0x38) 182 #define CTX_ELR_EL2 U(0x40) 183 #define CTX_ESR_EL2 U(0x48) 184 #define CTX_FAR_EL2 U(0x50) 185 #define CTX_HACR_EL2 U(0x58) 186 #define CTX_HCR_EL2 U(0x60) 187 #define CTX_HPFAR_EL2 U(0x68) 188 #define CTX_HSTR_EL2 U(0x70) 189 #define CTX_ICC_SRE_EL2 U(0x78) 190 #define CTX_ICH_HCR_EL2 U(0x80) 191 #define CTX_ICH_VMCR_EL2 U(0x88) 192 #define CTX_MAIR_EL2 U(0x90) 193 #define CTX_MDCR_EL2 U(0x98) 194 #define CTX_PMSCR_EL2 U(0xa0) 195 #define CTX_SCTLR_EL2 U(0xa8) 196 #define CTX_SPSR_EL2 U(0xb0) 197 #define CTX_SP_EL2 U(0xb8) 198 #define CTX_TCR_EL2 U(0xc0) 199 #define CTX_TPIDR_EL2 U(0xc8) 200 #define CTX_TTBR0_EL2 U(0xd0) 201 #define CTX_VBAR_EL2 U(0xd8) 202 #define CTX_VMPIDR_EL2 U(0xe0) 203 #define CTX_VPIDR_EL2 U(0xe8) 204 #define CTX_VTCR_EL2 U(0xf0) 205 #define CTX_VTTBR_EL2 U(0xf8) 206 207 // Only if MTE registers in use 208 #define CTX_TFSR_EL2 U(0x100) 209 210 // Starting with Armv8.6 211 #define CTX_HDFGRTR_EL2 U(0x108) 212 #define CTX_HAFGRTR_EL2 U(0x110) 213 #define CTX_HDFGWTR_EL2 U(0x118) 214 #define CTX_HFGITR_EL2 U(0x120) 215 #define CTX_HFGRTR_EL2 U(0x128) 216 #define CTX_HFGWTR_EL2 U(0x130) 217 #define CTX_CNTPOFF_EL2 U(0x138) 218 219 // Starting with Armv8.4 220 #define CTX_CONTEXTIDR_EL2 U(0x140) 221 #define CTX_TTBR1_EL2 U(0x148) 222 #define CTX_VDISR_EL2 U(0x150) 223 #define CTX_VSESR_EL2 U(0x158) 224 #define CTX_VNCR_EL2 U(0x160) 225 #define CTX_TRFCR_EL2 U(0x168) 226 227 // Starting with Armv8.5 228 #define CTX_SCXTNUM_EL2 U(0x170) 229 230 // Register for FEAT_HCX 231 #define CTX_HCRX_EL2 U(0x178) 232 233 // Starting with Armv8.9 234 #define CTX_TCR2_EL2 U(0x180) 235 #define CTX_POR_EL2 U(0x188) 236 #define CTX_PIRE0_EL2 U(0x190) 237 #define CTX_PIR_EL2 U(0x198) 238 #define CTX_S2PIR_EL2 U(0x1a0) 239 #define CTX_GCSCR_EL2 U(0x1a8) 240 #define CTX_GCSPR_EL2 U(0x1b0) 241 242 /* Align to the next 16 byte boundary */ 243 #define CTX_EL2_SYSREGS_END U(0x1c0) 244 245 #endif /* CTX_INCLUDE_EL2_REGS */ 246 247 /******************************************************************************* 248 * Constants that allow assembler code to access members of and the 'fp_regs' 249 * structure at their correct offsets. 250 ******************************************************************************/ 251 #if CTX_INCLUDE_EL2_REGS 252 # define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) 253 #else 254 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 255 #endif 256 #if CTX_INCLUDE_FPREGS 257 #define CTX_FP_Q0 U(0x0) 258 #define CTX_FP_Q1 U(0x10) 259 #define CTX_FP_Q2 U(0x20) 260 #define CTX_FP_Q3 U(0x30) 261 #define CTX_FP_Q4 U(0x40) 262 #define CTX_FP_Q5 U(0x50) 263 #define CTX_FP_Q6 U(0x60) 264 #define CTX_FP_Q7 U(0x70) 265 #define CTX_FP_Q8 U(0x80) 266 #define CTX_FP_Q9 U(0x90) 267 #define CTX_FP_Q10 U(0xa0) 268 #define CTX_FP_Q11 U(0xb0) 269 #define CTX_FP_Q12 U(0xc0) 270 #define CTX_FP_Q13 U(0xd0) 271 #define CTX_FP_Q14 U(0xe0) 272 #define CTX_FP_Q15 U(0xf0) 273 #define CTX_FP_Q16 U(0x100) 274 #define CTX_FP_Q17 U(0x110) 275 #define CTX_FP_Q18 U(0x120) 276 #define CTX_FP_Q19 U(0x130) 277 #define CTX_FP_Q20 U(0x140) 278 #define CTX_FP_Q21 U(0x150) 279 #define CTX_FP_Q22 U(0x160) 280 #define CTX_FP_Q23 U(0x170) 281 #define CTX_FP_Q24 U(0x180) 282 #define CTX_FP_Q25 U(0x190) 283 #define CTX_FP_Q26 U(0x1a0) 284 #define CTX_FP_Q27 U(0x1b0) 285 #define CTX_FP_Q28 U(0x1c0) 286 #define CTX_FP_Q29 U(0x1d0) 287 #define CTX_FP_Q30 U(0x1e0) 288 #define CTX_FP_Q31 U(0x1f0) 289 #define CTX_FP_FPSR U(0x200) 290 #define CTX_FP_FPCR U(0x208) 291 #if CTX_INCLUDE_AARCH32_REGS 292 #define CTX_FP_FPEXC32_EL2 U(0x210) 293 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 294 #else 295 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 296 #endif 297 #else 298 #define CTX_FPREGS_END U(0) 299 #endif 300 301 /******************************************************************************* 302 * Registers related to CVE-2018-3639 303 ******************************************************************************/ 304 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 305 #define CTX_CVE_2018_3639_DISABLE U(0) 306 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 307 308 /******************************************************************************* 309 * Registers related to ARMv8.3-PAuth. 310 ******************************************************************************/ 311 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 312 #if CTX_INCLUDE_PAUTH_REGS 313 #define CTX_PACIAKEY_LO U(0x0) 314 #define CTX_PACIAKEY_HI U(0x8) 315 #define CTX_PACIBKEY_LO U(0x10) 316 #define CTX_PACIBKEY_HI U(0x18) 317 #define CTX_PACDAKEY_LO U(0x20) 318 #define CTX_PACDAKEY_HI U(0x28) 319 #define CTX_PACDBKEY_LO U(0x30) 320 #define CTX_PACDBKEY_HI U(0x38) 321 #define CTX_PACGAKEY_LO U(0x40) 322 #define CTX_PACGAKEY_HI U(0x48) 323 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 324 #else 325 #define CTX_PAUTH_REGS_END U(0) 326 #endif /* CTX_INCLUDE_PAUTH_REGS */ 327 328 /******************************************************************************* 329 * Registers related to ARMv8.2-MPAM. 330 ******************************************************************************/ 331 #define CTX_MPAM_REGS_OFFSET (CTX_PAUTH_REGS_OFFSET + CTX_PAUTH_REGS_END) 332 #if CTX_INCLUDE_MPAM_REGS 333 #define CTX_MPAM2_EL2 U(0x0) 334 #define CTX_MPAMHCR_EL2 U(0x8) 335 #define CTX_MPAMVPM0_EL2 U(0x10) 336 #define CTX_MPAMVPM1_EL2 U(0x18) 337 #define CTX_MPAMVPM2_EL2 U(0x20) 338 #define CTX_MPAMVPM3_EL2 U(0x28) 339 #define CTX_MPAMVPM4_EL2 U(0x30) 340 #define CTX_MPAMVPM5_EL2 U(0x38) 341 #define CTX_MPAMVPM6_EL2 U(0x40) 342 #define CTX_MPAMVPM7_EL2 U(0x48) 343 #define CTX_MPAMVPMV_EL2 U(0x50) 344 #define CTX_MPAM_REGS_END U(0x60) 345 #else 346 #define CTX_MPAM_REGS_END U(0x0) 347 #endif /* CTX_INCLUDE_MPAM_REGS */ 348 349 /******************************************************************************* 350 * Registers initialised in a per-world context. 351 ******************************************************************************/ 352 #define CTX_CPTR_EL3 U(0x0) 353 #define CTX_ZCR_EL3 U(0x8) 354 #define CTX_MPAM3_EL3 U(0x10) 355 #define CTX_PERWORLD_EL3STATE_END U(0x18) 356 357 #ifndef __ASSEMBLER__ 358 359 #include <stdint.h> 360 361 #include <lib/cassert.h> 362 363 /* 364 * Common constants to help define the 'cpu_context' structure and its 365 * members below. 366 */ 367 #define DWORD_SHIFT U(3) 368 #define DEFINE_REG_STRUCT(name, num_regs) \ 369 typedef struct name { \ 370 uint64_t ctx_regs[num_regs]; \ 371 } __aligned(16) name##_t 372 373 /* Constants to determine the size of individual context structures */ 374 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 375 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 376 #if CTX_INCLUDE_EL2_REGS 377 # define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) 378 #endif 379 #if CTX_INCLUDE_FPREGS 380 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 381 #endif 382 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 383 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 384 #if CTX_INCLUDE_PAUTH_REGS 385 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 386 #endif 387 #if CTX_INCLUDE_MPAM_REGS 388 # define CTX_MPAM_REGS_ALL (CTX_MPAM_REGS_END >> DWORD_SHIFT) 389 #endif 390 391 /* 392 * AArch64 general purpose register context structure. Usually x0-x18, 393 * lr are saved as the compiler is expected to preserve the remaining 394 * callee saved registers if used by the C runtime and the assembler 395 * does not touch the remaining. But in case of world switch during 396 * exception handling, we need to save the callee registers too. 397 */ 398 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 399 400 /* 401 * AArch64 EL1 system register context structure for preserving the 402 * architectural state during world switches. 403 */ 404 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 405 406 407 /* 408 * AArch64 EL2 system register context structure for preserving the 409 * architectural state during world switches. 410 */ 411 #if CTX_INCLUDE_EL2_REGS 412 DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); 413 #endif 414 415 /* 416 * AArch64 floating point register context structure for preserving 417 * the floating point state during switches from one security state to 418 * another. 419 */ 420 #if CTX_INCLUDE_FPREGS 421 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 422 #endif 423 424 /* 425 * Miscellaneous registers used by EL3 firmware to maintain its state 426 * across exception entries and exits 427 */ 428 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 429 430 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 431 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 432 433 /* Registers associated to ARMv8.3-PAuth */ 434 #if CTX_INCLUDE_PAUTH_REGS 435 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 436 #endif 437 438 /* Registers associated to ARMv8.2 MPAM */ 439 #if CTX_INCLUDE_MPAM_REGS 440 DEFINE_REG_STRUCT(mpam, CTX_MPAM_REGS_ALL); 441 #endif 442 443 /* 444 * Macros to access members of any of the above structures using their 445 * offsets 446 */ 447 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 448 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 449 = (uint64_t) (val)) 450 451 /* 452 * Top-level context structure which is used by EL3 firmware to preserve 453 * the state of a core at the next lower EL in a given security state and 454 * save enough EL3 meta data to be able to return to that EL and security 455 * state. The context management library will be used to ensure that 456 * SP_EL3 always points to an instance of this structure at exception 457 * entry and exit. 458 */ 459 typedef struct cpu_context { 460 gp_regs_t gpregs_ctx; 461 el3_state_t el3state_ctx; 462 el1_sysregs_t el1_sysregs_ctx; 463 #if CTX_INCLUDE_EL2_REGS 464 el2_sysregs_t el2_sysregs_ctx; 465 #endif 466 #if CTX_INCLUDE_FPREGS 467 fp_regs_t fpregs_ctx; 468 #endif 469 cve_2018_3639_t cve_2018_3639_ctx; 470 #if CTX_INCLUDE_PAUTH_REGS 471 pauth_t pauth_ctx; 472 #endif 473 #if CTX_INCLUDE_MPAM_REGS 474 mpam_t mpam_ctx; 475 #endif 476 } cpu_context_t; 477 478 /* 479 * Per-World Context. 480 * It stores registers whose values can be shared across CPUs. 481 */ 482 typedef struct per_world_context { 483 uint64_t ctx_cptr_el3; 484 uint64_t ctx_zcr_el3; 485 uint64_t ctx_mpam3_el3; 486 } per_world_context_t; 487 488 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 489 490 /* Macros to access members of the 'cpu_context_t' structure */ 491 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 492 #if CTX_INCLUDE_FPREGS 493 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 494 #endif 495 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 496 #if CTX_INCLUDE_EL2_REGS 497 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 498 #endif 499 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 500 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 501 #if CTX_INCLUDE_PAUTH_REGS 502 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 503 #endif 504 #if CTX_INCLUDE_MPAM_REGS 505 # define get_mpam_ctx(h) (&((cpu_context_t *) h)->mpam_ctx) 506 #endif 507 508 /* 509 * Compile time assertions related to the 'cpu_context' structure to 510 * ensure that the assembler and the compiler view of the offsets of 511 * the structure members is the same. 512 */ 513 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 514 assert_core_context_gp_offset_mismatch); 515 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), 516 assert_core_context_el1_sys_offset_mismatch); 517 #if CTX_INCLUDE_EL2_REGS 518 CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), 519 assert_core_context_el2_sys_offset_mismatch); 520 #endif 521 #if CTX_INCLUDE_FPREGS 522 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), 523 assert_core_context_fp_offset_mismatch); 524 #endif 525 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 526 assert_core_context_el3state_offset_mismatch); 527 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 528 assert_core_context_cve_2018_3639_offset_mismatch); 529 #if CTX_INCLUDE_PAUTH_REGS 530 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 531 assert_core_context_pauth_offset_mismatch); 532 #endif 533 #if CTX_INCLUDE_MPAM_REGS 534 CASSERT(CTX_MPAM_REGS_OFFSET == __builtin_offsetof(cpu_context_t, mpam_ctx), 535 assert_core_context_mpam_offset_mismatch); 536 #endif 537 538 /* 539 * Helper macro to set the general purpose registers that correspond to 540 * parameters in an aapcs_64 call i.e. x0-x7 541 */ 542 #define set_aapcs_args0(ctx, x0) do { \ 543 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 544 } while (0) 545 #define set_aapcs_args1(ctx, x0, x1) do { \ 546 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 547 set_aapcs_args0(ctx, x0); \ 548 } while (0) 549 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 550 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 551 set_aapcs_args1(ctx, x0, x1); \ 552 } while (0) 553 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 554 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 555 set_aapcs_args2(ctx, x0, x1, x2); \ 556 } while (0) 557 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 558 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 559 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 560 } while (0) 561 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 562 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 563 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 564 } while (0) 565 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 566 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 567 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 568 } while (0) 569 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 570 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 571 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 572 } while (0) 573 574 /******************************************************************************* 575 * Function prototypes 576 ******************************************************************************/ 577 #if CTX_INCLUDE_FPREGS 578 void fpregs_context_save(fp_regs_t *regs); 579 void fpregs_context_restore(fp_regs_t *regs); 580 #endif 581 582 #endif /* __ASSEMBLER__ */ 583 584 #endif /* CONTEXT_H */ 585