1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Constants that allow assembler code to access members of and the 'gp_regs' 14 * structure at their correct offsets. 15 ******************************************************************************/ 16 #define CTX_GPREGS_OFFSET U(0x0) 17 #define CTX_GPREG_X0 U(0x0) 18 #define CTX_GPREG_X1 U(0x8) 19 #define CTX_GPREG_X2 U(0x10) 20 #define CTX_GPREG_X3 U(0x18) 21 #define CTX_GPREG_X4 U(0x20) 22 #define CTX_GPREG_X5 U(0x28) 23 #define CTX_GPREG_X6 U(0x30) 24 #define CTX_GPREG_X7 U(0x38) 25 #define CTX_GPREG_X8 U(0x40) 26 #define CTX_GPREG_X9 U(0x48) 27 #define CTX_GPREG_X10 U(0x50) 28 #define CTX_GPREG_X11 U(0x58) 29 #define CTX_GPREG_X12 U(0x60) 30 #define CTX_GPREG_X13 U(0x68) 31 #define CTX_GPREG_X14 U(0x70) 32 #define CTX_GPREG_X15 U(0x78) 33 #define CTX_GPREG_X16 U(0x80) 34 #define CTX_GPREG_X17 U(0x88) 35 #define CTX_GPREG_X18 U(0x90) 36 #define CTX_GPREG_X19 U(0x98) 37 #define CTX_GPREG_X20 U(0xa0) 38 #define CTX_GPREG_X21 U(0xa8) 39 #define CTX_GPREG_X22 U(0xb0) 40 #define CTX_GPREG_X23 U(0xb8) 41 #define CTX_GPREG_X24 U(0xc0) 42 #define CTX_GPREG_X25 U(0xc8) 43 #define CTX_GPREG_X26 U(0xd0) 44 #define CTX_GPREG_X27 U(0xd8) 45 #define CTX_GPREG_X28 U(0xe0) 46 #define CTX_GPREG_X29 U(0xe8) 47 #define CTX_GPREG_LR U(0xf0) 48 #define CTX_GPREG_SP_EL0 U(0xf8) 49 #define CTX_GPREGS_END U(0x100) 50 51 /******************************************************************************* 52 * Constants that allow assembler code to access members of and the 'el3_state' 53 * structure at their correct offsets. Note that some of the registers are only 54 * 32-bits wide but are stored as 64-bit values for convenience 55 ******************************************************************************/ 56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 57 #define CTX_SCR_EL3 U(0x0) 58 #define CTX_ESR_EL3 U(0x8) 59 #define CTX_RUNTIME_SP U(0x10) 60 #define CTX_SPSR_EL3 U(0x18) 61 #define CTX_ELR_EL3 U(0x20) 62 #define CTX_PMCR_EL0 U(0x28) 63 #define CTX_IS_IN_EL3 U(0x30) 64 #define CTX_CPTR_EL3 U(0x38) 65 #define CTX_ZCR_EL3 U(0x40) 66 #define CTX_MPAM3_EL3 U(0x48) 67 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 68 69 /******************************************************************************* 70 * Constants that allow assembler code to access members of and the 71 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 72 * registers are only 32-bits wide but are stored as 64-bit values for 73 * convenience 74 ******************************************************************************/ 75 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 76 #define CTX_SPSR_EL1 U(0x0) 77 #define CTX_ELR_EL1 U(0x8) 78 #define CTX_SCTLR_EL1 U(0x10) 79 #define CTX_TCR_EL1 U(0x18) 80 #define CTX_CPACR_EL1 U(0x20) 81 #define CTX_CSSELR_EL1 U(0x28) 82 #define CTX_SP_EL1 U(0x30) 83 #define CTX_ESR_EL1 U(0x38) 84 #define CTX_TTBR0_EL1 U(0x40) 85 #define CTX_TTBR1_EL1 U(0x48) 86 #define CTX_MAIR_EL1 U(0x50) 87 #define CTX_AMAIR_EL1 U(0x58) 88 #define CTX_ACTLR_EL1 U(0x60) 89 #define CTX_TPIDR_EL1 U(0x68) 90 #define CTX_TPIDR_EL0 U(0x70) 91 #define CTX_TPIDRRO_EL0 U(0x78) 92 #define CTX_PAR_EL1 U(0x80) 93 #define CTX_FAR_EL1 U(0x88) 94 #define CTX_AFSR0_EL1 U(0x90) 95 #define CTX_AFSR1_EL1 U(0x98) 96 #define CTX_CONTEXTIDR_EL1 U(0xa0) 97 #define CTX_VBAR_EL1 U(0xa8) 98 99 /* 100 * If the platform is AArch64-only, there is no need to save and restore these 101 * AArch32 registers. 102 */ 103 #if CTX_INCLUDE_AARCH32_REGS 104 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 105 #define CTX_SPSR_UND U(0xb8) 106 #define CTX_SPSR_IRQ U(0xc0) 107 #define CTX_SPSR_FIQ U(0xc8) 108 #define CTX_DACR32_EL2 U(0xd0) 109 #define CTX_IFSR32_EL2 U(0xd8) 110 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 111 #else 112 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 113 #endif /* CTX_INCLUDE_AARCH32_REGS */ 114 115 /* 116 * If the timer registers aren't saved and restored, we don't have to reserve 117 * space for them in the context 118 */ 119 #if NS_TIMER_SWITCH 120 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 121 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 122 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 123 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 124 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 125 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 126 #else 127 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 128 #endif /* NS_TIMER_SWITCH */ 129 130 #if CTX_INCLUDE_MTE_REGS 131 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 132 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 133 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 134 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 135 136 /* Align to the next 16 byte boundary */ 137 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 138 #else 139 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 140 #endif /* CTX_INCLUDE_MTE_REGS */ 141 142 /* 143 * End of system registers. 144 */ 145 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 146 147 /* 148 * EL2 register set 149 */ 150 151 #if CTX_INCLUDE_EL2_REGS 152 /* For later discussion 153 * ICH_AP0R<n>_EL2 154 * ICH_AP1R<n>_EL2 155 * AMEVCNTVOFF0<n>_EL2 156 * AMEVCNTVOFF1<n>_EL2 157 * ICH_LR<n>_EL2 158 */ 159 #define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 160 161 #define CTX_ACTLR_EL2 U(0x0) 162 #define CTX_AFSR0_EL2 U(0x8) 163 #define CTX_AFSR1_EL2 U(0x10) 164 #define CTX_AMAIR_EL2 U(0x18) 165 #define CTX_CNTHCTL_EL2 U(0x20) 166 #define CTX_CNTVOFF_EL2 U(0x28) 167 #define CTX_CPTR_EL2 U(0x30) 168 #define CTX_DBGVCR32_EL2 U(0x38) 169 #define CTX_ELR_EL2 U(0x40) 170 #define CTX_ESR_EL2 U(0x48) 171 #define CTX_FAR_EL2 U(0x50) 172 #define CTX_HACR_EL2 U(0x58) 173 #define CTX_HCR_EL2 U(0x60) 174 #define CTX_HPFAR_EL2 U(0x68) 175 #define CTX_HSTR_EL2 U(0x70) 176 #define CTX_ICC_SRE_EL2 U(0x78) 177 #define CTX_ICH_HCR_EL2 U(0x80) 178 #define CTX_ICH_VMCR_EL2 U(0x88) 179 #define CTX_MAIR_EL2 U(0x90) 180 #define CTX_MDCR_EL2 U(0x98) 181 #define CTX_PMSCR_EL2 U(0xa0) 182 #define CTX_SCTLR_EL2 U(0xa8) 183 #define CTX_SPSR_EL2 U(0xb0) 184 #define CTX_SP_EL2 U(0xb8) 185 #define CTX_TCR_EL2 U(0xc0) 186 #define CTX_TPIDR_EL2 U(0xc8) 187 #define CTX_TTBR0_EL2 U(0xd0) 188 #define CTX_VBAR_EL2 U(0xd8) 189 #define CTX_VMPIDR_EL2 U(0xe0) 190 #define CTX_VPIDR_EL2 U(0xe8) 191 #define CTX_VTCR_EL2 U(0xf0) 192 #define CTX_VTTBR_EL2 U(0xf8) 193 194 // Only if MTE registers in use 195 #define CTX_TFSR_EL2 U(0x100) 196 197 #define CTX_MPAM2_EL2 U(0x108) 198 #define CTX_MPAMHCR_EL2 U(0x110) 199 #define CTX_MPAMVPM0_EL2 U(0x118) 200 #define CTX_MPAMVPM1_EL2 U(0x120) 201 #define CTX_MPAMVPM2_EL2 U(0x128) 202 #define CTX_MPAMVPM3_EL2 U(0x130) 203 #define CTX_MPAMVPM4_EL2 U(0x138) 204 #define CTX_MPAMVPM5_EL2 U(0x140) 205 #define CTX_MPAMVPM6_EL2 U(0x148) 206 #define CTX_MPAMVPM7_EL2 U(0x150) 207 #define CTX_MPAMVPMV_EL2 U(0x158) 208 209 // Starting with Armv8.6 210 #define CTX_HDFGRTR_EL2 U(0x160) 211 #define CTX_HAFGRTR_EL2 U(0x168) 212 #define CTX_HDFGWTR_EL2 U(0x170) 213 #define CTX_HFGITR_EL2 U(0x178) 214 #define CTX_HFGRTR_EL2 U(0x180) 215 #define CTX_HFGWTR_EL2 U(0x188) 216 #define CTX_CNTPOFF_EL2 U(0x190) 217 218 // Starting with Armv8.4 219 #define CTX_CONTEXTIDR_EL2 U(0x198) 220 #define CTX_TTBR1_EL2 U(0x1a0) 221 #define CTX_VDISR_EL2 U(0x1a8) 222 #define CTX_VSESR_EL2 U(0x1b0) 223 #define CTX_VNCR_EL2 U(0x1b8) 224 #define CTX_TRFCR_EL2 U(0x1c0) 225 226 // Starting with Armv8.5 227 #define CTX_SCXTNUM_EL2 U(0x1c8) 228 229 // Register for FEAT_HCX 230 #define CTX_HCRX_EL2 U(0x1d0) 231 232 // Starting with Armv8.9 233 #define CTX_TCR2_EL2 U(0x1d8) 234 #define CTX_POR_EL2 U(0x1e0) 235 #define CTX_PIRE0_EL2 U(0x1e8) 236 #define CTX_PIR_EL2 U(0x1f0) 237 #define CTX_S2PIR_EL2 U(0x1f8) 238 #define CTX_GCSCR_EL2 U(0x200) 239 #define CTX_GCSPR_EL2 U(0x208) 240 241 /* Align to the next 16 byte boundary */ 242 #define CTX_EL2_SYSREGS_END U(0x210) 243 244 #endif /* CTX_INCLUDE_EL2_REGS */ 245 246 /******************************************************************************* 247 * Constants that allow assembler code to access members of and the 'fp_regs' 248 * structure at their correct offsets. 249 ******************************************************************************/ 250 #if CTX_INCLUDE_EL2_REGS 251 # define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) 252 #else 253 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 254 #endif 255 #if CTX_INCLUDE_FPREGS 256 #define CTX_FP_Q0 U(0x0) 257 #define CTX_FP_Q1 U(0x10) 258 #define CTX_FP_Q2 U(0x20) 259 #define CTX_FP_Q3 U(0x30) 260 #define CTX_FP_Q4 U(0x40) 261 #define CTX_FP_Q5 U(0x50) 262 #define CTX_FP_Q6 U(0x60) 263 #define CTX_FP_Q7 U(0x70) 264 #define CTX_FP_Q8 U(0x80) 265 #define CTX_FP_Q9 U(0x90) 266 #define CTX_FP_Q10 U(0xa0) 267 #define CTX_FP_Q11 U(0xb0) 268 #define CTX_FP_Q12 U(0xc0) 269 #define CTX_FP_Q13 U(0xd0) 270 #define CTX_FP_Q14 U(0xe0) 271 #define CTX_FP_Q15 U(0xf0) 272 #define CTX_FP_Q16 U(0x100) 273 #define CTX_FP_Q17 U(0x110) 274 #define CTX_FP_Q18 U(0x120) 275 #define CTX_FP_Q19 U(0x130) 276 #define CTX_FP_Q20 U(0x140) 277 #define CTX_FP_Q21 U(0x150) 278 #define CTX_FP_Q22 U(0x160) 279 #define CTX_FP_Q23 U(0x170) 280 #define CTX_FP_Q24 U(0x180) 281 #define CTX_FP_Q25 U(0x190) 282 #define CTX_FP_Q26 U(0x1a0) 283 #define CTX_FP_Q27 U(0x1b0) 284 #define CTX_FP_Q28 U(0x1c0) 285 #define CTX_FP_Q29 U(0x1d0) 286 #define CTX_FP_Q30 U(0x1e0) 287 #define CTX_FP_Q31 U(0x1f0) 288 #define CTX_FP_FPSR U(0x200) 289 #define CTX_FP_FPCR U(0x208) 290 #if CTX_INCLUDE_AARCH32_REGS 291 #define CTX_FP_FPEXC32_EL2 U(0x210) 292 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 293 #else 294 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 295 #endif 296 #else 297 #define CTX_FPREGS_END U(0) 298 #endif 299 300 /******************************************************************************* 301 * Registers related to CVE-2018-3639 302 ******************************************************************************/ 303 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 304 #define CTX_CVE_2018_3639_DISABLE U(0) 305 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 306 307 /******************************************************************************* 308 * Registers related to ARMv8.3-PAuth. 309 ******************************************************************************/ 310 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 311 #if CTX_INCLUDE_PAUTH_REGS 312 #define CTX_PACIAKEY_LO U(0x0) 313 #define CTX_PACIAKEY_HI U(0x8) 314 #define CTX_PACIBKEY_LO U(0x10) 315 #define CTX_PACIBKEY_HI U(0x18) 316 #define CTX_PACDAKEY_LO U(0x20) 317 #define CTX_PACDAKEY_HI U(0x28) 318 #define CTX_PACDBKEY_LO U(0x30) 319 #define CTX_PACDBKEY_HI U(0x38) 320 #define CTX_PACGAKEY_LO U(0x40) 321 #define CTX_PACGAKEY_HI U(0x48) 322 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 323 #else 324 #define CTX_PAUTH_REGS_END U(0) 325 #endif /* CTX_INCLUDE_PAUTH_REGS */ 326 327 #ifndef __ASSEMBLER__ 328 329 #include <stdint.h> 330 331 #include <lib/cassert.h> 332 333 /* 334 * Common constants to help define the 'cpu_context' structure and its 335 * members below. 336 */ 337 #define DWORD_SHIFT U(3) 338 #define DEFINE_REG_STRUCT(name, num_regs) \ 339 typedef struct name { \ 340 uint64_t ctx_regs[num_regs]; \ 341 } __aligned(16) name##_t 342 343 /* Constants to determine the size of individual context structures */ 344 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 345 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 346 #if CTX_INCLUDE_EL2_REGS 347 # define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) 348 #endif 349 #if CTX_INCLUDE_FPREGS 350 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 351 #endif 352 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 353 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 354 #if CTX_INCLUDE_PAUTH_REGS 355 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 356 #endif 357 358 /* 359 * AArch64 general purpose register context structure. Usually x0-x18, 360 * lr are saved as the compiler is expected to preserve the remaining 361 * callee saved registers if used by the C runtime and the assembler 362 * does not touch the remaining. But in case of world switch during 363 * exception handling, we need to save the callee registers too. 364 */ 365 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 366 367 /* 368 * AArch64 EL1 system register context structure for preserving the 369 * architectural state during world switches. 370 */ 371 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 372 373 374 /* 375 * AArch64 EL2 system register context structure for preserving the 376 * architectural state during world switches. 377 */ 378 #if CTX_INCLUDE_EL2_REGS 379 DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); 380 #endif 381 382 /* 383 * AArch64 floating point register context structure for preserving 384 * the floating point state during switches from one security state to 385 * another. 386 */ 387 #if CTX_INCLUDE_FPREGS 388 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 389 #endif 390 391 /* 392 * Miscellaneous registers used by EL3 firmware to maintain its state 393 * across exception entries and exits 394 */ 395 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 396 397 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 398 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 399 400 /* Registers associated to ARMv8.3-PAuth */ 401 #if CTX_INCLUDE_PAUTH_REGS 402 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 403 #endif 404 405 /* 406 * Macros to access members of any of the above structures using their 407 * offsets 408 */ 409 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 410 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 411 = (uint64_t) (val)) 412 413 /* 414 * Top-level context structure which is used by EL3 firmware to preserve 415 * the state of a core at the next lower EL in a given security state and 416 * save enough EL3 meta data to be able to return to that EL and security 417 * state. The context management library will be used to ensure that 418 * SP_EL3 always points to an instance of this structure at exception 419 * entry and exit. 420 */ 421 typedef struct cpu_context { 422 gp_regs_t gpregs_ctx; 423 el3_state_t el3state_ctx; 424 el1_sysregs_t el1_sysregs_ctx; 425 #if CTX_INCLUDE_EL2_REGS 426 el2_sysregs_t el2_sysregs_ctx; 427 #endif 428 #if CTX_INCLUDE_FPREGS 429 fp_regs_t fpregs_ctx; 430 #endif 431 cve_2018_3639_t cve_2018_3639_ctx; 432 #if CTX_INCLUDE_PAUTH_REGS 433 pauth_t pauth_ctx; 434 #endif 435 } cpu_context_t; 436 437 /* Macros to access members of the 'cpu_context_t' structure */ 438 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 439 #if CTX_INCLUDE_FPREGS 440 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 441 #endif 442 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 443 #if CTX_INCLUDE_EL2_REGS 444 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 445 #endif 446 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 447 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 448 #if CTX_INCLUDE_PAUTH_REGS 449 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 450 #endif 451 452 /* 453 * Compile time assertions related to the 'cpu_context' structure to 454 * ensure that the assembler and the compiler view of the offsets of 455 * the structure members is the same. 456 */ 457 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 458 assert_core_context_gp_offset_mismatch); 459 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), 460 assert_core_context_el1_sys_offset_mismatch); 461 #if CTX_INCLUDE_EL2_REGS 462 CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), 463 assert_core_context_el2_sys_offset_mismatch); 464 #endif 465 #if CTX_INCLUDE_FPREGS 466 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), 467 assert_core_context_fp_offset_mismatch); 468 #endif 469 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 470 assert_core_context_el3state_offset_mismatch); 471 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 472 assert_core_context_cve_2018_3639_offset_mismatch); 473 #if CTX_INCLUDE_PAUTH_REGS 474 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 475 assert_core_context_pauth_offset_mismatch); 476 #endif 477 478 /* 479 * Helper macro to set the general purpose registers that correspond to 480 * parameters in an aapcs_64 call i.e. x0-x7 481 */ 482 #define set_aapcs_args0(ctx, x0) do { \ 483 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 484 } while (0) 485 #define set_aapcs_args1(ctx, x0, x1) do { \ 486 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 487 set_aapcs_args0(ctx, x0); \ 488 } while (0) 489 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 490 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 491 set_aapcs_args1(ctx, x0, x1); \ 492 } while (0) 493 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 494 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 495 set_aapcs_args2(ctx, x0, x1, x2); \ 496 } while (0) 497 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 498 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 499 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 500 } while (0) 501 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 502 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 503 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 504 } while (0) 505 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 506 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 507 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 508 } while (0) 509 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 510 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 511 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 512 } while (0) 513 514 /******************************************************************************* 515 * Function prototypes 516 ******************************************************************************/ 517 void el1_sysregs_context_save(el1_sysregs_t *regs); 518 void el1_sysregs_context_restore(el1_sysregs_t *regs); 519 520 #if CTX_INCLUDE_FPREGS 521 void fpregs_context_save(fp_regs_t *regs); 522 void fpregs_context_restore(fp_regs_t *regs); 523 #endif 524 525 #endif /* __ASSEMBLER__ */ 526 527 #endif /* CONTEXT_H */ 528