1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/el3_runtime/context_el1.h> 11 #include <lib/el3_runtime/context_el2.h> 12 #include <lib/el3_runtime/cpu_data.h> 13 #include <lib/el3_runtime/simd_ctx.h> 14 #include <lib/utils_def.h> 15 16 /******************************************************************************* 17 * Constants that allow assembler code to access members of and the 'gp_regs' 18 * structure at their correct offsets. 19 ******************************************************************************/ 20 #define CTX_GPREGS_OFFSET U(0x0) 21 #define CTX_GPREG_X0 U(0x0) 22 #define CTX_GPREG_X1 U(0x8) 23 #define CTX_GPREG_X2 U(0x10) 24 #define CTX_GPREG_X3 U(0x18) 25 #define CTX_GPREG_X4 U(0x20) 26 #define CTX_GPREG_X5 U(0x28) 27 #define CTX_GPREG_X6 U(0x30) 28 #define CTX_GPREG_X7 U(0x38) 29 #define CTX_GPREG_X8 U(0x40) 30 #define CTX_GPREG_X9 U(0x48) 31 #define CTX_GPREG_X10 U(0x50) 32 #define CTX_GPREG_X11 U(0x58) 33 #define CTX_GPREG_X12 U(0x60) 34 #define CTX_GPREG_X13 U(0x68) 35 #define CTX_GPREG_X14 U(0x70) 36 #define CTX_GPREG_X15 U(0x78) 37 #define CTX_GPREG_X16 U(0x80) 38 #define CTX_GPREG_X17 U(0x88) 39 #define CTX_GPREG_X18 U(0x90) 40 #define CTX_GPREG_X19 U(0x98) 41 #define CTX_GPREG_X20 U(0xa0) 42 #define CTX_GPREG_X21 U(0xa8) 43 #define CTX_GPREG_X22 U(0xb0) 44 #define CTX_GPREG_X23 U(0xb8) 45 #define CTX_GPREG_X24 U(0xc0) 46 #define CTX_GPREG_X25 U(0xc8) 47 #define CTX_GPREG_X26 U(0xd0) 48 #define CTX_GPREG_X27 U(0xd8) 49 #define CTX_GPREG_X28 U(0xe0) 50 #define CTX_GPREG_X29 U(0xe8) 51 #define CTX_GPREG_LR U(0xf0) 52 #define CTX_GPREG_SP_EL0 U(0xf8) 53 #define CTX_GPREGS_END U(0x100) 54 55 /******************************************************************************* 56 * Constants that allow assembler code to access members of and the 'el3_state' 57 * structure at their correct offsets. Note that some of the registers are only 58 * 32-bits wide but are stored as 64-bit values for convenience 59 ******************************************************************************/ 60 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 61 #define CTX_SCR_EL3 U(0x0) 62 #define CTX_ESR_EL3 U(0x8) 63 #define CTX_RUNTIME_SP U(0x10) 64 #define CTX_SPSR_EL3 U(0x18) 65 #define CTX_ELR_EL3 U(0x20) 66 #define CTX_PMCR_EL0 U(0x28) 67 #define CTX_IS_IN_EL3 U(0x30) 68 #define CTX_MDCR_EL3 U(0x38) 69 /* Constants required in supporting nested exception in EL3 */ 70 #define CTX_SAVED_ELR_EL3 U(0x40) 71 /* 72 * General purpose flag, to save various EL3 states 73 * FFH mode : Used to identify if handling nested exception 74 * KFH mode : Used as counter value 75 */ 76 #define CTX_NESTED_EA_FLAG U(0x48) 77 #if FFH_SUPPORT 78 #define CTX_SAVED_ESR_EL3 U(0x50) 79 #define CTX_SAVED_SPSR_EL3 U(0x58) 80 #define CTX_SAVED_GPREG_LR U(0x60) 81 #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */ 82 #else 83 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 84 #endif /* FFH_SUPPORT */ 85 86 87 /******************************************************************************* 88 * Registers related to CVE-2018-3639 89 ******************************************************************************/ 90 #define CTX_CVE_2018_3639_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 91 #define CTX_CVE_2018_3639_DISABLE U(0) 92 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 93 94 /******************************************************************************* 95 * Registers related to ERRATA_SPECULATIVE_AT 96 * 97 * This is essential as with EL1 and EL2 context registers being decoupled, 98 * both will not be present for a given build configuration. 99 * As ERRATA_SPECULATIVE_AT errata requires SCTLR_EL1 and TCR_EL1 registers 100 * independent of the above logic, we need explicit context entries to be 101 * reserved for these registers. 102 * 103 * NOTE: Based on this we end up with following different configurations depending 104 * on the presence of errata and inclusion of EL1 or EL2 context. 105 * 106 * ============================================================================ 107 * | ERRATA_SPECULATIVE_AT | EL1 context| Memory allocation(Sctlr_el1,Tcr_el1)| 108 * ============================================================================ 109 * | 0 | 0 | None | 110 * | 0 | 1 | EL1 C-Context structure | 111 * | 1 | 0 | Errata Context Offset Entries | 112 * | 1 | 1 | Errata Context Offset Entries | 113 * ============================================================================ 114 * 115 * In the above table, when ERRATA_SPECULATIVE_AT=1, EL1_Context=0, it implies 116 * there is only EL2 context and memory for SCTLR_EL1 and TCR_EL1 registers is 117 * reserved explicitly under ERRATA_SPECULATIVE_AT build flag here. 118 * 119 * In situations when EL1_Context=1 and ERRATA_SPECULATIVE_AT=1, since SCTLR_EL1 120 * and TCR_EL1 registers will be modified under errata and it happens at the 121 * early in the codeflow prior to el1 context (save and restore operations), 122 * context memory still will be reserved under the errata logic here explicitly. 123 * These registers will not be part of EL1 context save & restore routines. 124 * 125 * Only when ERRATA_SPECULATIVE_AT=0, EL1_Context=1, for this combination, 126 * SCTLR_EL1 and TCR_EL1 will be part of EL1 context structure (context_el1.h) 127 * ----------------------------------------------------------------------------- 128 ******************************************************************************/ 129 #define CTX_ERRATA_SPEC_AT_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 130 #if ERRATA_SPECULATIVE_AT 131 #define CTX_ERRATA_SPEC_AT_SCTLR_EL1 U(0x0) 132 #define CTX_ERRATA_SPEC_AT_TCR_EL1 U(0x8) 133 #define CTX_ERRATA_SPEC_AT_END U(0x10) /* Align to the next 16 byte boundary */ 134 #else 135 #define CTX_ERRATA_SPEC_AT_END U(0x0) 136 #endif /* ERRATA_SPECULATIVE_AT */ 137 138 /******************************************************************************* 139 * Registers related to ARMv8.3-PAuth. 140 ******************************************************************************/ 141 #define CTX_PAUTH_REGS_OFFSET (CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_END) 142 #if CTX_INCLUDE_PAUTH_REGS 143 #define CTX_PACIAKEY_LO U(0x0) 144 #define CTX_PACIAKEY_HI U(0x8) 145 #define CTX_PACIBKEY_LO U(0x10) 146 #define CTX_PACIBKEY_HI U(0x18) 147 #define CTX_PACDAKEY_LO U(0x20) 148 #define CTX_PACDAKEY_HI U(0x28) 149 #define CTX_PACDBKEY_LO U(0x30) 150 #define CTX_PACDBKEY_HI U(0x38) 151 #define CTX_PACGAKEY_LO U(0x40) 152 #define CTX_PACGAKEY_HI U(0x48) 153 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 154 #else 155 #define CTX_PAUTH_REGS_END U(0) 156 #endif /* CTX_INCLUDE_PAUTH_REGS */ 157 158 /******************************************************************************* 159 * Registers initialised in a per-world context. 160 ******************************************************************************/ 161 #define CTX_CPTR_EL3 U(0x0) 162 #define CTX_ZCR_EL3 U(0x8) 163 #define CTX_MPAM3_EL3 U(0x10) 164 #define CTX_PERWORLD_EL3STATE_END U(0x18) 165 166 #ifndef __ASSEMBLER__ 167 168 #include <stdint.h> 169 170 #include <lib/cassert.h> 171 172 /* 173 * Common constants to help define the 'cpu_context' structure and its 174 * members below. 175 */ 176 #define DWORD_SHIFT U(3) 177 #define DEFINE_REG_STRUCT(name, num_regs) \ 178 typedef struct name { \ 179 uint64_t ctx_regs[num_regs]; \ 180 } __aligned(16) name##_t 181 182 /* Constants to determine the size of individual context structures */ 183 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 184 185 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 186 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 187 188 #if ERRATA_SPECULATIVE_AT 189 #define CTX_ERRATA_SPEC_AT_ALL (CTX_ERRATA_SPEC_AT_END >> DWORD_SHIFT) 190 #endif 191 #if CTX_INCLUDE_PAUTH_REGS 192 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 193 #endif 194 195 /* 196 * AArch64 general purpose register context structure. Usually x0-x18, 197 * lr are saved as the compiler is expected to preserve the remaining 198 * callee saved registers if used by the C runtime and the assembler 199 * does not touch the remaining. But in case of world switch during 200 * exception handling, we need to save the callee registers too. 201 */ 202 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 203 204 /* 205 * Miscellaneous registers used by EL3 firmware to maintain its state 206 * across exception entries and exits 207 */ 208 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 209 210 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 211 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 212 213 /* Registers associated to Errata_Speculative */ 214 #if ERRATA_SPECULATIVE_AT 215 DEFINE_REG_STRUCT(errata_speculative_at, CTX_ERRATA_SPEC_AT_ALL); 216 #endif 217 218 /* Registers associated to ARMv8.3-PAuth */ 219 #if CTX_INCLUDE_PAUTH_REGS 220 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 221 #endif 222 223 /* 224 * Macros to access members of any of the above structures using their 225 * offsets 226 */ 227 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 228 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 229 = (uint64_t) (val)) 230 231 /* 232 * Top-level context structure which is used by EL3 firmware to preserve 233 * the state of a core at the next lower EL in a given security state and 234 * save enough EL3 meta data to be able to return to that EL and security 235 * state. The context management library will be used to ensure that 236 * SP_EL3 always points to an instance of this structure at exception 237 * entry and exit. 238 */ 239 typedef struct cpu_context { 240 gp_regs_t gpregs_ctx; 241 el3_state_t el3state_ctx; 242 243 cve_2018_3639_t cve_2018_3639_ctx; 244 245 #if ERRATA_SPECULATIVE_AT 246 errata_speculative_at_t errata_speculative_at_ctx; 247 #endif 248 249 #if CTX_INCLUDE_PAUTH_REGS 250 pauth_t pauth_ctx; 251 #endif 252 253 el1_sysregs_t el1_sysregs_ctx; 254 255 #if CTX_INCLUDE_EL2_REGS 256 el2_sysregs_t el2_sysregs_ctx; 257 #endif 258 259 } cpu_context_t; 260 261 /* 262 * Per-World Context. 263 * It stores registers whose values can be shared across CPUs. 264 */ 265 typedef struct per_world_context { 266 uint64_t ctx_cptr_el3; 267 uint64_t ctx_zcr_el3; 268 uint64_t ctx_mpam3_el3; 269 } per_world_context_t; 270 271 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 272 273 /* Macros to access members of the 'cpu_context_t' structure */ 274 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 275 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 276 #if CTX_INCLUDE_EL2_REGS 277 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 278 #endif 279 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 280 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 281 282 #if ERRATA_SPECULATIVE_AT 283 #define get_errata_speculative_at_ctx(h) (&((cpu_context_t *) h)->errata_speculative_at_ctx) 284 #endif 285 286 #if CTX_INCLUDE_PAUTH_REGS 287 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 288 #endif 289 290 /* 291 * Compile time assertions related to the 'cpu_context' structure to 292 * ensure that the assembler and the compiler view of the offsets of 293 * the structure members is the same. 294 */ 295 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 296 assert_core_context_gp_offset_mismatch); 297 298 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 299 assert_core_context_el3state_offset_mismatch); 300 301 302 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 303 assert_core_context_cve_2018_3639_offset_mismatch); 304 305 #if ERRATA_SPECULATIVE_AT 306 CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx), 307 assert_core_context_errata_speculative_at_offset_mismatch); 308 #endif 309 310 #if CTX_INCLUDE_PAUTH_REGS 311 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 312 assert_core_context_pauth_offset_mismatch); 313 #endif /* CTX_INCLUDE_PAUTH_REGS */ 314 315 /* 316 * Helper macro to set the general purpose registers that correspond to 317 * parameters in an aapcs_64 call i.e. x0-x7 318 */ 319 #define set_aapcs_args0(ctx, x0) do { \ 320 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 321 } while (0) 322 #define set_aapcs_args1(ctx, x0, x1) do { \ 323 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 324 set_aapcs_args0(ctx, x0); \ 325 } while (0) 326 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 327 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 328 set_aapcs_args1(ctx, x0, x1); \ 329 } while (0) 330 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 331 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 332 set_aapcs_args2(ctx, x0, x1, x2); \ 333 } while (0) 334 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 335 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 336 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 337 } while (0) 338 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 339 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 340 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 341 } while (0) 342 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 343 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 344 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 345 } while (0) 346 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 347 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 348 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 349 } while (0) 350 351 /******************************************************************************* 352 * Function prototypes 353 ******************************************************************************/ 354 #if CTX_INCLUDE_FPREGS 355 void fpregs_context_save(simd_regs_t *regs); 356 void fpregs_context_restore(simd_regs_t *regs); 357 #endif 358 359 #endif /* __ASSEMBLER__ */ 360 361 #endif /* CONTEXT_H */ 362