1 /* 2 * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/el3_runtime/context_el1.h> 11 #include <lib/el3_runtime/context_el2.h> 12 #include <lib/el3_runtime/cpu_data.h> 13 #include <lib/utils_def.h> 14 15 /******************************************************************************* 16 * Constants that allow assembler code to access members of and the 'gp_regs' 17 * structure at their correct offsets. 18 ******************************************************************************/ 19 #define CTX_GPREGS_OFFSET U(0x0) 20 #define CTX_GPREG_X0 U(0x0) 21 #define CTX_GPREG_X1 U(0x8) 22 #define CTX_GPREG_X2 U(0x10) 23 #define CTX_GPREG_X3 U(0x18) 24 #define CTX_GPREG_X4 U(0x20) 25 #define CTX_GPREG_X5 U(0x28) 26 #define CTX_GPREG_X6 U(0x30) 27 #define CTX_GPREG_X7 U(0x38) 28 #define CTX_GPREG_X8 U(0x40) 29 #define CTX_GPREG_X9 U(0x48) 30 #define CTX_GPREG_X10 U(0x50) 31 #define CTX_GPREG_X11 U(0x58) 32 #define CTX_GPREG_X12 U(0x60) 33 #define CTX_GPREG_X13 U(0x68) 34 #define CTX_GPREG_X14 U(0x70) 35 #define CTX_GPREG_X15 U(0x78) 36 #define CTX_GPREG_X16 U(0x80) 37 #define CTX_GPREG_X17 U(0x88) 38 #define CTX_GPREG_X18 U(0x90) 39 #define CTX_GPREG_X19 U(0x98) 40 #define CTX_GPREG_X20 U(0xa0) 41 #define CTX_GPREG_X21 U(0xa8) 42 #define CTX_GPREG_X22 U(0xb0) 43 #define CTX_GPREG_X23 U(0xb8) 44 #define CTX_GPREG_X24 U(0xc0) 45 #define CTX_GPREG_X25 U(0xc8) 46 #define CTX_GPREG_X26 U(0xd0) 47 #define CTX_GPREG_X27 U(0xd8) 48 #define CTX_GPREG_X28 U(0xe0) 49 #define CTX_GPREG_X29 U(0xe8) 50 #define CTX_GPREG_LR U(0xf0) 51 #define CTX_GPREG_SP_EL0 U(0xf8) 52 #define CTX_GPREGS_END U(0x100) 53 54 /******************************************************************************* 55 * Constants that allow assembler code to access members of and the 'el3_state' 56 * structure at their correct offsets. Note that some of the registers are only 57 * 32-bits wide but are stored as 64-bit values for convenience 58 ******************************************************************************/ 59 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 60 #define CTX_SCR_EL3 U(0x0) 61 #define CTX_ESR_EL3 U(0x8) 62 #define CTX_RUNTIME_SP U(0x10) 63 #define CTX_SPSR_EL3 U(0x18) 64 #define CTX_ELR_EL3 U(0x20) 65 #define CTX_PMCR_EL0 U(0x28) 66 #define CTX_IS_IN_EL3 U(0x30) 67 #define CTX_MDCR_EL3 U(0x38) 68 /* Constants required in supporting nested exception in EL3 */ 69 #define CTX_SAVED_ELR_EL3 U(0x40) 70 /* 71 * General purpose flag, to save various EL3 states 72 * FFH mode : Used to identify if handling nested exception 73 * KFH mode : Used as counter value 74 */ 75 #define CTX_NESTED_EA_FLAG U(0x48) 76 #if FFH_SUPPORT 77 #define CTX_SAVED_ESR_EL3 U(0x50) 78 #define CTX_SAVED_SPSR_EL3 U(0x58) 79 #define CTX_SAVED_GPREG_LR U(0x60) 80 #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */ 81 #else 82 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 83 #endif /* FFH_SUPPORT */ 84 85 /******************************************************************************* 86 * Constants that allow assembler code to access members of and the 'fp_regs' 87 * structure at their correct offsets. 88 ******************************************************************************/ 89 # define CTX_FPREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 90 #if CTX_INCLUDE_FPREGS 91 #define CTX_FP_Q0 U(0x0) 92 #define CTX_FP_Q1 U(0x10) 93 #define CTX_FP_Q2 U(0x20) 94 #define CTX_FP_Q3 U(0x30) 95 #define CTX_FP_Q4 U(0x40) 96 #define CTX_FP_Q5 U(0x50) 97 #define CTX_FP_Q6 U(0x60) 98 #define CTX_FP_Q7 U(0x70) 99 #define CTX_FP_Q8 U(0x80) 100 #define CTX_FP_Q9 U(0x90) 101 #define CTX_FP_Q10 U(0xa0) 102 #define CTX_FP_Q11 U(0xb0) 103 #define CTX_FP_Q12 U(0xc0) 104 #define CTX_FP_Q13 U(0xd0) 105 #define CTX_FP_Q14 U(0xe0) 106 #define CTX_FP_Q15 U(0xf0) 107 #define CTX_FP_Q16 U(0x100) 108 #define CTX_FP_Q17 U(0x110) 109 #define CTX_FP_Q18 U(0x120) 110 #define CTX_FP_Q19 U(0x130) 111 #define CTX_FP_Q20 U(0x140) 112 #define CTX_FP_Q21 U(0x150) 113 #define CTX_FP_Q22 U(0x160) 114 #define CTX_FP_Q23 U(0x170) 115 #define CTX_FP_Q24 U(0x180) 116 #define CTX_FP_Q25 U(0x190) 117 #define CTX_FP_Q26 U(0x1a0) 118 #define CTX_FP_Q27 U(0x1b0) 119 #define CTX_FP_Q28 U(0x1c0) 120 #define CTX_FP_Q29 U(0x1d0) 121 #define CTX_FP_Q30 U(0x1e0) 122 #define CTX_FP_Q31 U(0x1f0) 123 #define CTX_FP_FPSR U(0x200) 124 #define CTX_FP_FPCR U(0x208) 125 #if CTX_INCLUDE_AARCH32_REGS 126 #define CTX_FP_FPEXC32_EL2 U(0x210) 127 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 128 #else 129 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 130 #endif /* CTX_INCLUDE_AARCH32_REGS */ 131 #else 132 #define CTX_FPREGS_END U(0) 133 #endif /* CTX_INCLUDE_FPREGS */ 134 135 /******************************************************************************* 136 * Registers related to CVE-2018-3639 137 ******************************************************************************/ 138 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 139 #define CTX_CVE_2018_3639_DISABLE U(0) 140 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 141 142 /******************************************************************************* 143 * Registers related to ERRATA_SPECULATIVE_AT 144 * 145 * This is essential as with EL1 and EL2 context registers being decoupled, 146 * both will not be present for a given build configuration. 147 * As ERRATA_SPECULATIVE_AT errata requires SCTLR_EL1 and TCR_EL1 registers 148 * independent of the above logic, we need explicit context entries to be 149 * reserved for these registers. 150 * 151 * NOTE: Based on this we end up with following different configurations depending 152 * on the presence of errata and inclusion of EL1 or EL2 context. 153 * 154 * ============================================================================ 155 * | ERRATA_SPECULATIVE_AT | EL1 context| Memory allocation(Sctlr_el1,Tcr_el1)| 156 * ============================================================================ 157 * | 0 | 0 | None | 158 * | 0 | 1 | EL1 C-Context structure | 159 * | 1 | 0 | Errata Context Offset Entries | 160 * | 1 | 1 | Errata Context Offset Entries | 161 * ============================================================================ 162 * 163 * In the above table, when ERRATA_SPECULATIVE_AT=1, EL1_Context=0, it implies 164 * there is only EL2 context and memory for SCTLR_EL1 and TCR_EL1 registers is 165 * reserved explicitly under ERRATA_SPECULATIVE_AT build flag here. 166 * 167 * In situations when EL1_Context=1 and ERRATA_SPECULATIVE_AT=1, since SCTLR_EL1 168 * and TCR_EL1 registers will be modified under errata and it happens at the 169 * early in the codeflow prior to el1 context (save and restore operations), 170 * context memory still will be reserved under the errata logic here explicitly. 171 * These registers will not be part of EL1 context save & restore routines. 172 * 173 * Only when ERRATA_SPECULATIVE_AT=0, EL1_Context=1, for this combination, 174 * SCTLR_EL1 and TCR_EL1 will be part of EL1 context structure (context_el1.h) 175 * ----------------------------------------------------------------------------- 176 ******************************************************************************/ 177 #define CTX_ERRATA_SPEC_AT_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 178 #if ERRATA_SPECULATIVE_AT 179 #define CTX_ERRATA_SPEC_AT_SCTLR_EL1 U(0x0) 180 #define CTX_ERRATA_SPEC_AT_TCR_EL1 U(0x8) 181 #define CTX_ERRATA_SPEC_AT_END U(0x10) /* Align to the next 16 byte boundary */ 182 #else 183 #define CTX_ERRATA_SPEC_AT_END U(0x0) 184 #endif /* ERRATA_SPECULATIVE_AT */ 185 186 /******************************************************************************* 187 * Registers related to ARMv8.3-PAuth. 188 ******************************************************************************/ 189 #define CTX_PAUTH_REGS_OFFSET (CTX_ERRATA_SPEC_AT_OFFSET + CTX_ERRATA_SPEC_AT_END) 190 #if CTX_INCLUDE_PAUTH_REGS 191 #define CTX_PACIAKEY_LO U(0x0) 192 #define CTX_PACIAKEY_HI U(0x8) 193 #define CTX_PACIBKEY_LO U(0x10) 194 #define CTX_PACIBKEY_HI U(0x18) 195 #define CTX_PACDAKEY_LO U(0x20) 196 #define CTX_PACDAKEY_HI U(0x28) 197 #define CTX_PACDBKEY_LO U(0x30) 198 #define CTX_PACDBKEY_HI U(0x38) 199 #define CTX_PACGAKEY_LO U(0x40) 200 #define CTX_PACGAKEY_HI U(0x48) 201 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 202 #else 203 #define CTX_PAUTH_REGS_END U(0) 204 #endif /* CTX_INCLUDE_PAUTH_REGS */ 205 206 /******************************************************************************* 207 * Registers initialised in a per-world context. 208 ******************************************************************************/ 209 #define CTX_CPTR_EL3 U(0x0) 210 #define CTX_ZCR_EL3 U(0x8) 211 #define CTX_MPAM3_EL3 U(0x10) 212 #define CTX_PERWORLD_EL3STATE_END U(0x18) 213 214 #ifndef __ASSEMBLER__ 215 216 #include <stdint.h> 217 218 #include <lib/cassert.h> 219 220 /* 221 * Common constants to help define the 'cpu_context' structure and its 222 * members below. 223 */ 224 #define DWORD_SHIFT U(3) 225 #define DEFINE_REG_STRUCT(name, num_regs) \ 226 typedef struct name { \ 227 uint64_t ctx_regs[num_regs]; \ 228 } __aligned(16) name##_t 229 230 /* Constants to determine the size of individual context structures */ 231 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 232 233 #if CTX_INCLUDE_FPREGS 234 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 235 #endif 236 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 237 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 238 239 #if ERRATA_SPECULATIVE_AT 240 #define CTX_ERRATA_SPEC_AT_ALL (CTX_ERRATA_SPEC_AT_END >> DWORD_SHIFT) 241 #endif 242 #if CTX_INCLUDE_PAUTH_REGS 243 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 244 #endif 245 246 /* 247 * AArch64 general purpose register context structure. Usually x0-x18, 248 * lr are saved as the compiler is expected to preserve the remaining 249 * callee saved registers if used by the C runtime and the assembler 250 * does not touch the remaining. But in case of world switch during 251 * exception handling, we need to save the callee registers too. 252 */ 253 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 254 255 /* 256 * AArch64 floating point register context structure for preserving 257 * the floating point state during switches from one security state to 258 * another. 259 */ 260 #if CTX_INCLUDE_FPREGS 261 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 262 #endif 263 264 /* 265 * Miscellaneous registers used by EL3 firmware to maintain its state 266 * across exception entries and exits 267 */ 268 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 269 270 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 271 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 272 273 /* Registers associated to Errata_Speculative */ 274 #if ERRATA_SPECULATIVE_AT 275 DEFINE_REG_STRUCT(errata_speculative_at, CTX_ERRATA_SPEC_AT_ALL); 276 #endif 277 278 /* Registers associated to ARMv8.3-PAuth */ 279 #if CTX_INCLUDE_PAUTH_REGS 280 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 281 #endif 282 283 /* 284 * Macros to access members of any of the above structures using their 285 * offsets 286 */ 287 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 288 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 289 = (uint64_t) (val)) 290 291 /* 292 * Top-level context structure which is used by EL3 firmware to preserve 293 * the state of a core at the next lower EL in a given security state and 294 * save enough EL3 meta data to be able to return to that EL and security 295 * state. The context management library will be used to ensure that 296 * SP_EL3 always points to an instance of this structure at exception 297 * entry and exit. 298 */ 299 typedef struct cpu_context { 300 gp_regs_t gpregs_ctx; 301 el3_state_t el3state_ctx; 302 303 #if CTX_INCLUDE_FPREGS 304 fp_regs_t fpregs_ctx; 305 #endif 306 cve_2018_3639_t cve_2018_3639_ctx; 307 308 #if ERRATA_SPECULATIVE_AT 309 errata_speculative_at_t errata_speculative_at_ctx; 310 #endif 311 312 #if CTX_INCLUDE_PAUTH_REGS 313 pauth_t pauth_ctx; 314 #endif 315 316 el1_sysregs_t el1_sysregs_ctx; 317 318 #if CTX_INCLUDE_EL2_REGS 319 el2_sysregs_t el2_sysregs_ctx; 320 #endif 321 322 } cpu_context_t; 323 324 /* 325 * Per-World Context. 326 * It stores registers whose values can be shared across CPUs. 327 */ 328 typedef struct per_world_context { 329 uint64_t ctx_cptr_el3; 330 uint64_t ctx_zcr_el3; 331 uint64_t ctx_mpam3_el3; 332 } per_world_context_t; 333 334 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 335 336 /* Macros to access members of the 'cpu_context_t' structure */ 337 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 338 #if CTX_INCLUDE_FPREGS 339 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 340 #endif 341 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 342 #if CTX_INCLUDE_EL2_REGS 343 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 344 #endif 345 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 346 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 347 348 #if ERRATA_SPECULATIVE_AT 349 #define get_errata_speculative_at_ctx(h) (&((cpu_context_t *) h)->errata_speculative_at_ctx) 350 #endif 351 352 #if CTX_INCLUDE_PAUTH_REGS 353 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 354 #endif 355 356 /* 357 * Compile time assertions related to the 'cpu_context' structure to 358 * ensure that the assembler and the compiler view of the offsets of 359 * the structure members is the same. 360 */ 361 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 362 assert_core_context_gp_offset_mismatch); 363 364 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 365 assert_core_context_el3state_offset_mismatch); 366 367 #if CTX_INCLUDE_FPREGS 368 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), 369 assert_core_context_fp_offset_mismatch); 370 #endif /* CTX_INCLUDE_FPREGS */ 371 372 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 373 assert_core_context_cve_2018_3639_offset_mismatch); 374 375 #if ERRATA_SPECULATIVE_AT 376 CASSERT(CTX_ERRATA_SPEC_AT_OFFSET == __builtin_offsetof(cpu_context_t, errata_speculative_at_ctx), 377 assert_core_context_errata_speculative_at_offset_mismatch); 378 #endif 379 380 #if CTX_INCLUDE_PAUTH_REGS 381 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 382 assert_core_context_pauth_offset_mismatch); 383 #endif /* CTX_INCLUDE_PAUTH_REGS */ 384 385 /* 386 * Helper macro to set the general purpose registers that correspond to 387 * parameters in an aapcs_64 call i.e. x0-x7 388 */ 389 #define set_aapcs_args0(ctx, x0) do { \ 390 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 391 } while (0) 392 #define set_aapcs_args1(ctx, x0, x1) do { \ 393 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 394 set_aapcs_args0(ctx, x0); \ 395 } while (0) 396 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 397 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 398 set_aapcs_args1(ctx, x0, x1); \ 399 } while (0) 400 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 401 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 402 set_aapcs_args2(ctx, x0, x1, x2); \ 403 } while (0) 404 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 405 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 406 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 407 } while (0) 408 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 409 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 410 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 411 } while (0) 412 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 413 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 414 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 415 } while (0) 416 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 417 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 418 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 419 } while (0) 420 421 /******************************************************************************* 422 * Function prototypes 423 ******************************************************************************/ 424 #if CTX_INCLUDE_FPREGS 425 void fpregs_context_save(fp_regs_t *regs); 426 void fpregs_context_restore(fp_regs_t *regs); 427 #endif 428 429 #endif /* __ASSEMBLER__ */ 430 431 #endif /* CONTEXT_H */ 432