1 /* 2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************************* 13 * Constants that allow assembler code to access members of and the 'gp_regs' 14 * structure at their correct offsets. 15 ******************************************************************************/ 16 #define CTX_GPREGS_OFFSET U(0x0) 17 #define CTX_GPREG_X0 U(0x0) 18 #define CTX_GPREG_X1 U(0x8) 19 #define CTX_GPREG_X2 U(0x10) 20 #define CTX_GPREG_X3 U(0x18) 21 #define CTX_GPREG_X4 U(0x20) 22 #define CTX_GPREG_X5 U(0x28) 23 #define CTX_GPREG_X6 U(0x30) 24 #define CTX_GPREG_X7 U(0x38) 25 #define CTX_GPREG_X8 U(0x40) 26 #define CTX_GPREG_X9 U(0x48) 27 #define CTX_GPREG_X10 U(0x50) 28 #define CTX_GPREG_X11 U(0x58) 29 #define CTX_GPREG_X12 U(0x60) 30 #define CTX_GPREG_X13 U(0x68) 31 #define CTX_GPREG_X14 U(0x70) 32 #define CTX_GPREG_X15 U(0x78) 33 #define CTX_GPREG_X16 U(0x80) 34 #define CTX_GPREG_X17 U(0x88) 35 #define CTX_GPREG_X18 U(0x90) 36 #define CTX_GPREG_X19 U(0x98) 37 #define CTX_GPREG_X20 U(0xa0) 38 #define CTX_GPREG_X21 U(0xa8) 39 #define CTX_GPREG_X22 U(0xb0) 40 #define CTX_GPREG_X23 U(0xb8) 41 #define CTX_GPREG_X24 U(0xc0) 42 #define CTX_GPREG_X25 U(0xc8) 43 #define CTX_GPREG_X26 U(0xd0) 44 #define CTX_GPREG_X27 U(0xd8) 45 #define CTX_GPREG_X28 U(0xe0) 46 #define CTX_GPREG_X29 U(0xe8) 47 #define CTX_GPREG_LR U(0xf0) 48 #define CTX_GPREG_SP_EL0 U(0xf8) 49 #define CTX_GPREGS_END U(0x100) 50 51 /******************************************************************************* 52 * Constants that allow assembler code to access members of and the 'el3_state' 53 * structure at their correct offsets. Note that some of the registers are only 54 * 32-bits wide but are stored as 64-bit values for convenience 55 ******************************************************************************/ 56 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 57 #define CTX_SCR_EL3 U(0x0) 58 #define CTX_ESR_EL3 U(0x8) 59 #define CTX_RUNTIME_SP U(0x10) 60 #define CTX_SPSR_EL3 U(0x18) 61 #define CTX_ELR_EL3 U(0x20) 62 #define CTX_PMCR_EL0 U(0x28) 63 #define CTX_EL3STATE_END U(0x30) 64 65 /******************************************************************************* 66 * Constants that allow assembler code to access members of and the 67 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 68 * registers are only 32-bits wide but are stored as 64-bit values for 69 * convenience 70 ******************************************************************************/ 71 #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 72 #define CTX_SPSR_EL1 U(0x0) 73 #define CTX_ELR_EL1 U(0x8) 74 #define CTX_SCTLR_EL1 U(0x10) 75 #define CTX_ACTLR_EL1 U(0x18) 76 #define CTX_CPACR_EL1 U(0x20) 77 #define CTX_CSSELR_EL1 U(0x28) 78 #define CTX_SP_EL1 U(0x30) 79 #define CTX_ESR_EL1 U(0x38) 80 #define CTX_TTBR0_EL1 U(0x40) 81 #define CTX_TTBR1_EL1 U(0x48) 82 #define CTX_MAIR_EL1 U(0x50) 83 #define CTX_AMAIR_EL1 U(0x58) 84 #define CTX_TCR_EL1 U(0x60) 85 #define CTX_TPIDR_EL1 U(0x68) 86 #define CTX_TPIDR_EL0 U(0x70) 87 #define CTX_TPIDRRO_EL0 U(0x78) 88 #define CTX_PAR_EL1 U(0x80) 89 #define CTX_FAR_EL1 U(0x88) 90 #define CTX_AFSR0_EL1 U(0x90) 91 #define CTX_AFSR1_EL1 U(0x98) 92 #define CTX_CONTEXTIDR_EL1 U(0xa0) 93 #define CTX_VBAR_EL1 U(0xa8) 94 95 /* 96 * If the platform is AArch64-only, there is no need to save and restore these 97 * AArch32 registers. 98 */ 99 #if CTX_INCLUDE_AARCH32_REGS 100 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 101 #define CTX_SPSR_UND U(0xb8) 102 #define CTX_SPSR_IRQ U(0xc0) 103 #define CTX_SPSR_FIQ U(0xc8) 104 #define CTX_DACR32_EL2 U(0xd0) 105 #define CTX_IFSR32_EL2 U(0xd8) 106 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 107 #else 108 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 109 #endif /* CTX_INCLUDE_AARCH32_REGS */ 110 111 /* 112 * If the timer registers aren't saved and restored, we don't have to reserve 113 * space for them in the context 114 */ 115 #if NS_TIMER_SWITCH 116 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 117 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 118 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 119 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 120 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 121 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 122 #else 123 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 124 #endif /* NS_TIMER_SWITCH */ 125 126 #if CTX_INCLUDE_MTE_REGS 127 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 128 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 129 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 130 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 131 132 /* Align to the next 16 byte boundary */ 133 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 134 #else 135 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 136 #endif /* CTX_INCLUDE_MTE_REGS */ 137 138 /* 139 * S-EL2 register set 140 */ 141 142 #if CTX_INCLUDE_EL2_REGS 143 /* For later discussion 144 * ICH_AP0R<n>_EL2 145 * ICH_AP1R<n>_EL2 146 * AMEVCNTVOFF0<n>_EL2 147 * AMEVCNTVOFF1<n>_EL2 148 * ICH_LR<n>_EL2 149 */ 150 #define CTX_ACTLR_EL2 (CTX_MTE_REGS_END + U(0x0)) 151 #define CTX_AFSR0_EL2 (CTX_MTE_REGS_END + U(0x8)) 152 #define CTX_AFSR1_EL2 (CTX_MTE_REGS_END + U(0x10)) 153 #define CTX_AMAIR_EL2 (CTX_MTE_REGS_END + U(0x18)) 154 #define CTX_CNTHCTL_EL2 (CTX_MTE_REGS_END + U(0x20)) 155 #define CTX_CNTHP_CTL_EL2 (CTX_MTE_REGS_END + U(0x28)) 156 #define CTX_CNTHP_CVAL_EL2 (CTX_MTE_REGS_END + U(0x30)) 157 #define CTX_CNTHP_TVAL_EL2 (CTX_MTE_REGS_END + U(0x38)) 158 #define CTX_CNTPOFF_EL2 (CTX_MTE_REGS_END + U(0x40)) 159 #define CTX_CNTVOFF_EL2 (CTX_MTE_REGS_END + U(0x48)) 160 #define CTX_CPTR_EL2 (CTX_MTE_REGS_END + U(0x50)) 161 #define CTX_DBGVCR32_EL2 (CTX_MTE_REGS_END + U(0x58)) 162 #define CTX_ELR_EL2 (CTX_MTE_REGS_END + U(0x60)) 163 #define CTX_ESR_EL2 (CTX_MTE_REGS_END + U(0x68)) 164 #define CTX_FAR_EL2 (CTX_MTE_REGS_END + U(0x70)) 165 #define CTX_FPEXC32_EL2 (CTX_MTE_REGS_END + U(0x78)) 166 #define CTX_HACR_EL2 (CTX_MTE_REGS_END + U(0x80)) 167 #define CTX_HAFGRTR_EL2 (CTX_MTE_REGS_END + U(0x88)) 168 #define CTX_HCR_EL2 (CTX_MTE_REGS_END + U(0x90)) 169 #define CTX_HDFGRTR_EL2 (CTX_MTE_REGS_END + U(0x98)) 170 #define CTX_HDFGWTR_EL2 (CTX_MTE_REGS_END + U(0xA0)) 171 #define CTX_HFGITR_EL2 (CTX_MTE_REGS_END + U(0xA8)) 172 #define CTX_HFGRTR_EL2 (CTX_MTE_REGS_END + U(0xB0)) 173 #define CTX_HFGWTR_EL2 (CTX_MTE_REGS_END + U(0xB8)) 174 #define CTX_HPFAR_EL2 (CTX_MTE_REGS_END + U(0xC0)) 175 #define CTX_HSTR_EL2 (CTX_MTE_REGS_END + U(0xC8)) 176 #define CTX_ICC_SRE_EL2 (CTX_MTE_REGS_END + U(0xD0)) 177 #define CTX_ICH_EISR_EL2 (CTX_MTE_REGS_END + U(0xD8)) 178 #define CTX_ICH_ELRSR_EL2 (CTX_MTE_REGS_END + U(0xE0)) 179 #define CTX_ICH_HCR_EL2 (CTX_MTE_REGS_END + U(0xE8)) 180 #define CTX_ICH_MISR_EL2 (CTX_MTE_REGS_END + U(0xF0)) 181 #define CTX_ICH_VMCR_EL2 (CTX_MTE_REGS_END + U(0xF8)) 182 #define CTX_ICH_VTR_EL2 (CTX_MTE_REGS_END + U(0x100)) 183 #define CTX_MAIR_EL2 (CTX_MTE_REGS_END + U(0x108)) 184 #define CTX_MDCR_EL2 (CTX_MTE_REGS_END + U(0x110)) 185 #define CTX_MPAM2_EL2 (CTX_MTE_REGS_END + U(0x118)) 186 #define CTX_MPAMHCR_EL2 (CTX_MTE_REGS_END + U(0x120)) 187 #define CTX_MPAMVPM0_EL2 (CTX_MTE_REGS_END + U(0x128)) 188 #define CTX_MPAMVPM1_EL2 (CTX_MTE_REGS_END + U(0x130)) 189 #define CTX_MPAMVPM2_EL2 (CTX_MTE_REGS_END + U(0x138)) 190 #define CTX_MPAMVPM3_EL2 (CTX_MTE_REGS_END + U(0x140)) 191 #define CTX_MPAMVPM4_EL2 (CTX_MTE_REGS_END + U(0x148)) 192 #define CTX_MPAMVPM5_EL2 (CTX_MTE_REGS_END + U(0x150)) 193 #define CTX_MPAMVPM6_EL2 (CTX_MTE_REGS_END + U(0x158)) 194 #define CTX_MPAMVPM7_EL2 (CTX_MTE_REGS_END + U(0x160)) 195 #define CTX_MPAMVPMV_EL2 (CTX_MTE_REGS_END + U(0x168)) 196 #define CTX_RMR_EL2 (CTX_MTE_REGS_END + U(0x170)) 197 #define CTX_SCTLR_EL2 (CTX_MTE_REGS_END + U(0x178)) 198 #define CTX_SPSR_EL2 (CTX_MTE_REGS_END + U(0x180)) 199 #define CTX_SP_EL2 (CTX_MTE_REGS_END + U(0x188)) 200 #define CTX_TCR_EL2 (CTX_MTE_REGS_END + U(0x190)) 201 #define CTX_TPIDR_EL2 (CTX_MTE_REGS_END + U(0x198)) 202 #define CTX_TTBR0_EL2 (CTX_MTE_REGS_END + U(0x1A0)) 203 #define CTX_VBAR_EL2 (CTX_MTE_REGS_END + U(0x1A8)) 204 #define CTX_VMPIDR_EL2 (CTX_MTE_REGS_END + U(0x1B0)) 205 #define CTX_VPIDR_EL2 (CTX_MTE_REGS_END + U(0x1B8)) 206 #define CTX_VTCR_EL2 (CTX_MTE_REGS_END + U(0x1C0)) 207 #define CTX_VTTBR_EL2 (CTX_MTE_REGS_END + U(0x1C8)) 208 #define CTX_ZCR_EL2 (CTX_MTE_REGS_END + U(0x1B0)) 209 210 /* Align to the next 16 byte boundary */ 211 #define CTX_EL2_REGS_END (CTX_MTE_REGS_END + U(0x1C0)) 212 #else 213 #define CTX_EL2_REGS_END CTX_MTE_REGS_END 214 #endif /* CTX_INCLUDE_EL2_REGS */ 215 216 /* 217 * End of system registers. 218 */ 219 #define CTX_SYSREGS_END CTX_EL2_REGS_END 220 221 /******************************************************************************* 222 * Constants that allow assembler code to access members of and the 'fp_regs' 223 * structure at their correct offsets. 224 ******************************************************************************/ 225 #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) 226 #if CTX_INCLUDE_FPREGS 227 #define CTX_FP_Q0 U(0x0) 228 #define CTX_FP_Q1 U(0x10) 229 #define CTX_FP_Q2 U(0x20) 230 #define CTX_FP_Q3 U(0x30) 231 #define CTX_FP_Q4 U(0x40) 232 #define CTX_FP_Q5 U(0x50) 233 #define CTX_FP_Q6 U(0x60) 234 #define CTX_FP_Q7 U(0x70) 235 #define CTX_FP_Q8 U(0x80) 236 #define CTX_FP_Q9 U(0x90) 237 #define CTX_FP_Q10 U(0xa0) 238 #define CTX_FP_Q11 U(0xb0) 239 #define CTX_FP_Q12 U(0xc0) 240 #define CTX_FP_Q13 U(0xd0) 241 #define CTX_FP_Q14 U(0xe0) 242 #define CTX_FP_Q15 U(0xf0) 243 #define CTX_FP_Q16 U(0x100) 244 #define CTX_FP_Q17 U(0x110) 245 #define CTX_FP_Q18 U(0x120) 246 #define CTX_FP_Q19 U(0x130) 247 #define CTX_FP_Q20 U(0x140) 248 #define CTX_FP_Q21 U(0x150) 249 #define CTX_FP_Q22 U(0x160) 250 #define CTX_FP_Q23 U(0x170) 251 #define CTX_FP_Q24 U(0x180) 252 #define CTX_FP_Q25 U(0x190) 253 #define CTX_FP_Q26 U(0x1a0) 254 #define CTX_FP_Q27 U(0x1b0) 255 #define CTX_FP_Q28 U(0x1c0) 256 #define CTX_FP_Q29 U(0x1d0) 257 #define CTX_FP_Q30 U(0x1e0) 258 #define CTX_FP_Q31 U(0x1f0) 259 #define CTX_FP_FPSR U(0x200) 260 #define CTX_FP_FPCR U(0x208) 261 #if CTX_INCLUDE_AARCH32_REGS 262 #define CTX_FP_FPEXC32_EL2 U(0x210) 263 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 264 #else 265 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 266 #endif 267 #else 268 #define CTX_FPREGS_END U(0) 269 #endif 270 271 /******************************************************************************* 272 * Registers related to CVE-2018-3639 273 ******************************************************************************/ 274 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 275 #define CTX_CVE_2018_3639_DISABLE U(0) 276 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 277 278 /******************************************************************************* 279 * Registers related to ARMv8.3-PAuth. 280 ******************************************************************************/ 281 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 282 #if CTX_INCLUDE_PAUTH_REGS 283 #define CTX_PACIAKEY_LO U(0x0) 284 #define CTX_PACIAKEY_HI U(0x8) 285 #define CTX_PACIBKEY_LO U(0x10) 286 #define CTX_PACIBKEY_HI U(0x18) 287 #define CTX_PACDAKEY_LO U(0x20) 288 #define CTX_PACDAKEY_HI U(0x28) 289 #define CTX_PACDBKEY_LO U(0x30) 290 #define CTX_PACDBKEY_HI U(0x38) 291 #define CTX_PACGAKEY_LO U(0x40) 292 #define CTX_PACGAKEY_HI U(0x48) 293 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 294 #else 295 #define CTX_PAUTH_REGS_END U(0) 296 #endif /* CTX_INCLUDE_PAUTH_REGS */ 297 298 #ifndef __ASSEMBLER__ 299 300 #include <stdint.h> 301 302 #include <lib/cassert.h> 303 304 /* 305 * Common constants to help define the 'cpu_context' structure and its 306 * members below. 307 */ 308 #define DWORD_SHIFT U(3) 309 #define DEFINE_REG_STRUCT(name, num_regs) \ 310 typedef struct name { \ 311 uint64_t ctx_regs[num_regs]; \ 312 } __aligned(16) name##_t 313 314 /* Constants to determine the size of individual context structures */ 315 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 316 #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) 317 #if CTX_INCLUDE_FPREGS 318 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 319 #endif 320 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 321 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 322 #if CTX_INCLUDE_PAUTH_REGS 323 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 324 #endif 325 326 /* 327 * AArch64 general purpose register context structure. Usually x0-x18, 328 * lr are saved as the compiler is expected to preserve the remaining 329 * callee saved registers if used by the C runtime and the assembler 330 * does not touch the remaining. But in case of world switch during 331 * exception handling, we need to save the callee registers too. 332 */ 333 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 334 335 /* 336 * AArch64 EL1/EL2 system register context structure for preserving the 337 * architectural state during world switches. 338 */ 339 DEFINE_REG_STRUCT(sys_regs, CTX_SYSREG_ALL); 340 341 /* 342 * AArch64 floating point register context structure for preserving 343 * the floating point state during switches from one security state to 344 * another. 345 */ 346 #if CTX_INCLUDE_FPREGS 347 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 348 #endif 349 350 /* 351 * Miscellaneous registers used by EL3 firmware to maintain its state 352 * across exception entries and exits 353 */ 354 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 355 356 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 357 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 358 359 /* Registers associated to ARMv8.3-PAuth */ 360 #if CTX_INCLUDE_PAUTH_REGS 361 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 362 #endif 363 364 /* 365 * Macros to access members of any of the above structures using their 366 * offsets 367 */ 368 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 369 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 370 = (uint64_t) (val)) 371 372 /* 373 * Top-level context structure which is used by EL3 firmware to 374 * preserve the state of a core at EL1 in one of the two security 375 * states and save enough EL3 meta data to be able to return to that 376 * EL and security state. The context management library will be used 377 * to ensure that SP_EL3 always points to an instance of this 378 * structure at exception entry and exit. Each instance will 379 * correspond to either the secure or the non-secure state. 380 */ 381 typedef struct cpu_context { 382 gp_regs_t gpregs_ctx; 383 el3_state_t el3state_ctx; 384 sys_regs_t sysregs_ctx; 385 #if CTX_INCLUDE_FPREGS 386 fp_regs_t fpregs_ctx; 387 #endif 388 cve_2018_3639_t cve_2018_3639_ctx; 389 #if CTX_INCLUDE_PAUTH_REGS 390 pauth_t pauth_ctx; 391 #endif 392 } cpu_context_t; 393 394 /* Macros to access members of the 'cpu_context_t' structure */ 395 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 396 #if CTX_INCLUDE_FPREGS 397 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 398 #endif 399 #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) 400 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 401 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 402 #if CTX_INCLUDE_PAUTH_REGS 403 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 404 #endif 405 406 /* 407 * Compile time assertions related to the 'cpu_context' structure to 408 * ensure that the assembler and the compiler view of the offsets of 409 * the structure members is the same. 410 */ 411 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ 412 assert_core_context_gp_offset_mismatch); 413 CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ 414 assert_core_context_sys_offset_mismatch); 415 #if CTX_INCLUDE_FPREGS 416 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ 417 assert_core_context_fp_offset_mismatch); 418 #endif 419 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ 420 assert_core_context_el3state_offset_mismatch); 421 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), \ 422 assert_core_context_cve_2018_3639_offset_mismatch); 423 #if CTX_INCLUDE_PAUTH_REGS 424 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), \ 425 assert_core_context_pauth_offset_mismatch); 426 #endif 427 428 /* 429 * Helper macro to set the general purpose registers that correspond to 430 * parameters in an aapcs_64 call i.e. x0-x7 431 */ 432 #define set_aapcs_args0(ctx, x0) do { \ 433 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 434 } while (0) 435 #define set_aapcs_args1(ctx, x0, x1) do { \ 436 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 437 set_aapcs_args0(ctx, x0); \ 438 } while (0) 439 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 440 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 441 set_aapcs_args1(ctx, x0, x1); \ 442 } while (0) 443 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 444 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 445 set_aapcs_args2(ctx, x0, x1, x2); \ 446 } while (0) 447 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 448 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 449 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 450 } while (0) 451 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 452 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 453 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 454 } while (0) 455 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 456 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 457 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 458 } while (0) 459 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 460 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 461 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 462 } while (0) 463 464 /******************************************************************************* 465 * Function prototypes 466 ******************************************************************************/ 467 void el1_sysregs_context_save(sys_regs_t *regs); 468 void el1_sysregs_context_restore(sys_regs_t *regs); 469 470 #if CTX_INCLUDE_EL2_REGS 471 void el2_sysregs_context_save(sys_regs_t *regs); 472 void el2_sysregs_context_restore(sys_regs_t *regs); 473 #endif 474 475 #if CTX_INCLUDE_FPREGS 476 void fpregs_context_save(fp_regs_t *regs); 477 void fpregs_context_restore(fp_regs_t *regs); 478 #endif 479 480 #endif /* __ASSEMBLER__ */ 481 482 #endif /* CONTEXT_H */ 483