1*51247ccbSGovindraj Raja /* 2*51247ccbSGovindraj Raja * Copyright (c) 2025, Arm Limited. All rights reserved. 3*51247ccbSGovindraj Raja * 4*51247ccbSGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*51247ccbSGovindraj Raja */ 6*51247ccbSGovindraj Raja 7*51247ccbSGovindraj Raja #ifndef VEYMONT_H 8*51247ccbSGovindraj Raja #define VEYMONT_H 9*51247ccbSGovindraj Raja 10*51247ccbSGovindraj Raja #define VEYMONT_MIDR U(0x410FD9A0) 11*51247ccbSGovindraj Raja 12*51247ccbSGovindraj Raja /******************************************************************************* 13*51247ccbSGovindraj Raja * CPU Extended Control register specific definitions 14*51247ccbSGovindraj Raja ******************************************************************************/ 15*51247ccbSGovindraj Raja #define VEYMONT_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16*51247ccbSGovindraj Raja 17*51247ccbSGovindraj Raja /******************************************************************************* 18*51247ccbSGovindraj Raja * CPU Power Control register specific definitions 19*51247ccbSGovindraj Raja ******************************************************************************/ 20*51247ccbSGovindraj Raja #define VEYMONT_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*51247ccbSGovindraj Raja #define VEYMONT_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22*51247ccbSGovindraj Raja 23*51247ccbSGovindraj Raja #endif /* VEYMONT_H */ 24*51247ccbSGovindraj Raja 25